On Mon, Jun 4, 2018 at 12:44 PM, Haren Myneni wrote:
> On 06/03/2018 05:41 PM, Stewart Smith wrote:
>> Haren Myneni writes:
>>> On 06/01/2018 12:41 AM, Stewart Smith wrote:
Haren Myneni writes:
> NX increments readOffset by FIFO size in receive FIFO control register
> when CRB is re
On 06/03/2018 09:08 PM, Stewart Smith wrote:
> Haren Myneni writes:
>> On 06/03/2018 05:41 PM, Stewart Smith wrote:
>>> Haren Myneni writes:
On 06/01/2018 12:41 AM, Stewart Smith wrote:
> Haren Myneni writes:
>> NX increments readOffset by FIFO size in receive FIFO control register
Haren Myneni writes:
> On 06/03/2018 05:41 PM, Stewart Smith wrote:
>> Haren Myneni writes:
>>> On 06/01/2018 12:41 AM, Stewart Smith wrote:
Haren Myneni writes:
> NX increments readOffset by FIFO size in receive FIFO control register
> when CRB is read. But the index in RxFIFO has
On 06/03/2018 05:41 PM, Stewart Smith wrote:
> Haren Myneni writes:
>> On 06/01/2018 12:41 AM, Stewart Smith wrote:
>>> Haren Myneni writes:
NX increments readOffset by FIFO size in receive FIFO control register
when CRB is read. But the index in RxFIFO has to match with the
corres
On 06/03/2018 03:48 AM, Michael Ellerman wrote:
> Hi Haren,
>
> Haren Myneni writes:
>>
>> NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
>> which is not related to paste request. The current paste function
>> returns failure for the successful request when this bit is se
On Sat, Jun 02, 2018 at 01:40:46AM +1000, Michael Ellerman wrote:
> Sam Bobroff writes:
>
> > As EEH event handling progresses, a cumulative result of type
> > pci_ers_result is built up by (some of) the eeh_report_*() functions
> > using either:
> > if (rc == PCI_ERS_RESULT_NEED_RESET) *res
Haren Myneni writes:
> On 06/01/2018 12:41 AM, Stewart Smith wrote:
>> Haren Myneni writes:
>>> NX increments readOffset by FIFO size in receive FIFO control register
>>> when CRB is read. But the index in RxFIFO has to match with the
>>> corresponding entry in FIFO maintained by VAS in kernel. O
On Mon, May 21, 2018 at 01:29:11PM +0200, Florian Weimer wrote:
> On 05/20/2018 09:11 PM, Ram Pai wrote:
> >Florian,
> >
> > Does the following patch fix the problem for you? Just like x86
> > I am enabling all keys in the UAMOR register during
> > initialization itself. Hence any key
[Testing delayed due to internal SAN problems.]
mobility/numa: Ensure that numa_update_cpu_topology() can not be
entered multiple times concurrently. It may be accessed through
many different paths / concurrent work functions, and the lock
ordering may be difficult to ensure otherwise.
Signed-of
[Testing delayed due to internal SAN problems.]
powerpc/dlpar: Provide hotplug CPU 'readd by index' operation to
support LPAR Post Migration state updates. When such changes are
invoked by the PowerPC 'mobility' code, they will be queued up so
that modifications to CPU properties will take place
[Testing delayed due to internal SAN problems.]
migration/dlpar: This patch adds function dlpar_queue_action()
which will add information about a CPU/Memory 'readd' operation
according to resource type, action code, and DRC index. Initial
usage is for the 'readd' CPU and Memory blocks identified
[Testing delayed due to internal SAN problems.]
powerpc/cpu: Modify dlpar_cpu_add and dlpar_cpu_remove to allow the
skipping of DRC index acquire or release operations during the CPU
add or remove operations. This is intended to support subsequent
changes to provide a 'CPU readd' operation.
Sign
[Testing delayed due to internal SAN problems.]
The migration of LPARs across Power systems affects many attributes
including that of the associativity of CPUs. The patches in this
set execute when a system is coming up fresh upon a migration target.
They are intended to,
* Recognize changes to
Hi all,
Commit
cb3d6759a93c ("powerpc/64s: Enable barrier_nospec based on firmware settings")
is missing a Signed-off-by from its author.
--
Cheers,
Stephen Rothwell
pgpzQZTbuOqcx.pgp
Description: OpenPGP digital signature
On Friday 18 May 2018 01:05 PM, Anju T Sudhakar wrote:
Call trace observed while running perf-fuzzer:
[ 329.228068] CPU: 43 PID: 9088 Comm: perf_fuzzer Not tainted
4.13.0-32-generic #35~lp1746225
[ 329.228070] task: c03f776ac900 task.stack: c03f77728000
[ 329.228071] NIP: c000
When the masked interrupt handler clears MSR[EE] for an interrupt in
the PACA_IRQ_MUST_HARD_MASK set, it does not set PACA_IRQ_HARD_DIS.
This makes them get out of synch.
With that taken into account, it's only low level irq manipulation
(and interrupt entry before reconcile) where they can be out
Hi Haren,
Haren Myneni writes:
>
> NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
> which is not related to paste request. The current paste function
> returns failure for the successful request when this bit is set.
> So mask this bit and check the proper return status.
Greg KH writes:
> On Sat, Jun 02, 2018 at 09:08:45PM +1000, Michael Ellerman wrote:
>> Hi Greg,
>>
>> Please queue up this series of patches for 4.9 if you have no objections.
>>
>> The first one is not a backport but a fix for a previous backport.
>
> Looks good, all now queued up, thanks.
Th
On Sun, Jun 03, 2018 at 11:21:45AM +0200, Greg Kroah-Hartman wrote:
> On Sat, Jun 02, 2018 at 10:55:31PM +0200, Christophe Leroy wrote:
> >
> >
> > On 06/02/2018 03:21 PM, Greg Kroah-Hartman wrote:
> > > On Thu, May 31, 2018 at 08:54:52AM +, Christophe Leroy wrote:
> > > > [ Upstream commit a
On Sat, Jun 02, 2018 at 10:55:31PM +0200, Christophe Leroy wrote:
>
>
> On 06/02/2018 03:21 PM, Greg Kroah-Hartman wrote:
> > On Thu, May 31, 2018 at 08:54:52AM +, Christophe Leroy wrote:
> > > [ Upstream commit a3286f05bc5a5bc7fc73a9783ec89de78fcd07f8 ]
> > >
> > > In preparation for the fo
On 06/02/2018 03:21 PM, Greg Kroah-Hartman wrote:
On Thu, May 31, 2018 at 08:54:52AM +, Christophe Leroy wrote:
[ Upstream commit a3286f05bc5a5bc7fc73a9783ec89de78fcd07f8 ]
In preparation for the following patch which will enhance 'slices'
for supporting PPC32 in order to fix an issue on
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