On Fri, 01 Jun 2018 23:22:27 +1000
Michael Ellerman wrote:
> Masahiro Yamada writes:
> > 2018-06-01 19:34 GMT+09:00 Michael Ellerman :
> ...
> >
> > Could you update your branch, please?
>
> Done.
>
> I've only pushed the first three patches this time, to avoid any
> confusion. Hopefully :
Now that the PowerMac via-pmu driver supports m68k PowerBooks,
switch over to that driver and remove the via-pmu68k driver.
Don't call pmu_shutdown() or pmu_restart() on early PowerBooks:
the PMU device found in these PowerBooks isn't supported.
Cc: Geert Uytterhoeven
Tested-by: Stan Johnson
Si
On most PowerPC Macs, the PMU driver uses the shift register and
IO port B from a single VIA chip.
On 68k and early PowerPC PowerBooks, the driver uses the shift register
from one VIA chip together with IO port B from another.
Replace via with via1 and via2 to accommodate this. For the
CONFIG_PPC
Some of the event counters are overloaded which makes it very
difficult to interpret their values.
Counter 0 is supposed to report CB1 interrupts but it can also count
PMU_INT_WAITING_CHARGER events.
Counter 1 is supposed to report GPIO interrupts but it can also count
other events (depending upo
Replace an open-coded ffs() with the function call.
Simplify an if-else cascade using a switch statement.
Correct a typo and an indentation issue.
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
drivers/macintosh/via-pmu.c | 35 ++-
1 file changed, 18 inser
Put #ifdefs around the Open Firmware, xmon, interrupt dispatch,
battery and suspend code. Add the necessary interrupt handling to
support m68k PowerBooks.
The pmu_kind value is available to userspace using the
PMU_IOC_GET_MODEL ioctl. It is not clear yet what hardware classes
are be needed to desc
Now that the 68k Mac port has adopted the via-pmu driver, it must access
the PMU RTC using the appropriate command format. The same code can now
be used for both m68k and powerpc.
Replace the RTC code that's duplicated in arch/powerpc and arch/m68k
with common RTC accessors for Cuda and PMU device
At present, CONFIG_ADB_PMU depends on CONFIG_PPC_PMAC. When this gets
relaxed to CONFIG_PPC_PMAC || CONFIG_MAC, those Kconfig symbols with
implicit deps on PPC_PMAC will need explicit deps. Add them now.
No functional change.
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
drivers/macinto
On 68k Macs, the via/vias pointer can't be used to determine whether
the PMU driver has been initialized. For portability, add a new state
to indicate that via_find_pmu() succeeded.
After via_find_pmu() executes, testing vias == NULL is equivalent to
testing via == NULL. Replace these tests with p
Clearing the interrupt flag twice in succession creates a theoretical
race condition. Fix this.
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
drivers/macintosh/via-pmu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index 9c
Add missing in_8() accessors to init_pmu() and pmu_sr_intr().
This fixes several sparse warnings:
drivers/macintosh/via-pmu.c:536:29: warning: dereference of noderef expression
drivers/macintosh/via-pmu.c:537:33: warning: dereference of noderef expression
drivers/macintosh/via-pmu.c:1455:17: warni
This series of patches has the following aims.
1) Eliminate duplicated code. Linux presently has two drivers for
the 68HC05-based PMU devices found in Macs: via-pmu and via-pmu68k.
There's no value in having separate PMU drivers for each architecture.
2) Avoid further work on via-pmu68k tha
The pmu_init() function has the __init qualifier, but the ops struct
that holds a pointer to it does not. This causes a build warning.
The driver works fine because the pointer is only dereferenced early.
The function is so small that there's negligible benefit from using
the __init qualifier. Rem
On Fri, Jun 1, 2018 at 2:54 PM, Gautham R Shenoy
wrote:
> Hi Balbir,
>
> Thanks for reviewing the patch!
>
> On Fri, Jun 01, 2018 at 12:51:05AM +1000, Balbir Singh wrote:
>> On Thu, May 31, 2018 at 10:15 PM, Gautham R. Shenoy
>
> [..snip..]
>> >
>> > +static u64 get_snooze_timeout(struct cpuidle_
On Thu, 31 May 2018 15:39:03 +0530
"Naveen N. Rao" wrote:
> Masami Hiramatsu wrote:
> > On Tue, 29 May 2018 18:06:02 +0530
> > "Naveen N. Rao" wrote:
> >
> >> We already have an arch-independent way to set the instruction pointer
> >> with instruction_pointer_set(). Using this allows us to get
On Fri, Jun 01, 2018 at 08:52:27AM +1000, Nicholas Piggin wrote:
> On Fri, 01 Jun 2018 00:22:21 +1000
> Michael Ellerman wrote:
> > Nicholas Piggin writes:
> > > - p->save_area[index].esid = 0;
> > > - p->save_area[index].vsid = cpu_to_be64(mk_vsid_data(ea, ssize, flags));
> > > - p->save_area[in
On 06/01/2018 12:41 AM, Stewart Smith wrote:
> Haren Myneni writes:
>> NX increments readOffset by FIFO size in receive FIFO control register
>> when CRB is read. But the index in RxFIFO has to match with the
>> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
>> may be proces
/commits/Akshay-Adiga/powernv-cpuidle-Add-support-for-new-idle-state-device-tree-format/20180601-202708
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-allmodconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce
On Wed, 2018-05-30 at 12:32:25 UTC, "Aneesh Kumar K.V" wrote:
> Fix the below crash on BookE 64. pgtable_page_dtor expects struct page *arg.
>
> Also call the destructor on non book3s platforms correctly. This free up the
> split ptl locks correctly if we had allocated them before.
>
> Call Trace
On Tue, 2018-05-29 at 19:20:01 UTC, Mathieu Malaterre wrote:
> In commit eae5f709a4d7 ("powerpc: Add __printf verification to
> prom_printf") __printf attribute was added to prom_printf(), which
> means GCC started warning about type/format mismatches. As part of that
> commit we changed some "%lx"
On Fri, 2018-05-25 at 03:48:34 UTC, Josh Poimboeuf wrote:
> The toc field in the mod_arch_specific struct isn't actually used
> anywhere, so remove it.
>
> Also the ftrace-specific fields are now common between 32-bit and
> 64-bit, so simplify the struct definition a bit by moving them out of
> th
On Fri, 2018-05-25 at 02:11:45 UTC, Thiago Jung Bauermann wrote:
> This test verifies that the AMR, IAMR and UAMOR are being written to a
> process' core file.
>
> Signed-off-by: Thiago Jung Bauermann
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/39b91dd625f15438859204a489ab
On Fri, 2018-05-25 at 02:11:44 UTC, Thiago Jung Bauermann wrote:
> This test exercises read and write access to the AMR, IAMR and UAMOR.
>
> Signed-off-by: Thiago Jung Bauermann
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/1f7256e7dddef49acf9f6c9fe3f935
cheers
On Fri, 2018-05-18 at 09:42:23 UTC, Vaibhav Jain wrote:
> From: Vaibhav Jain
>
> Currently we see a kernel-oops reported on Power-9 while attaching a
> context to an AFU, with radix-mode and sysfs attr 'prefault_mode' set
> to anything other than 'none'. The backtrace of the oops is of this
> for
On Tue, 2018-05-22 at 09:08:20 UTC, "Aneesh Kumar K.V" wrote:
> arch/powerpc/kernel/stacktrace.c: In function
> âsave_stack_trace_tsk_reliableâ:
> arch/powerpc/kernel/stacktrace.c:176:28: error: âkretprobe_trampolineâ
> undeclared (first use in this function); did you mean
> âis_ftrace
On Wed, 2018-05-16 at 12:02:14 UTC, Akshay Adiga wrote:
> Init all present cpus for deep states instead of "all possible" cpus.
> Init fails if the possible cpu is gaurded. Resulting in making only
> non-deep states available for cpuidle/hotplug.
>
> Signed-off-by: Akshay Adiga
Applied to powerp
On Tue, 2018-05-08 at 05:00:24 UTC, Madhavan Srinivasan wrote:
> Comment explanning the raw event code encoding for Power8 was
> moved to isa207_common.h file when re-factoring the code to
> support power9. But then Power9 pmu branched out due to changes
> specific to power9. So move the encoding c
On Tue, 2018-04-17 at 05:11:02 UTC, Vaibhav Jain wrote:
> APC virtual machines arent used on POWER-9 chips and are already
> disabled in on-chip CAPP. They also need to be disabled on the PSL via
> 'PSL Data Send Control Register' by setting bit(47). This forces the
> PSL to send commands to CAPP w
move feature-fixups related stuff from synch.h to synch-ftr.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/atomic.h | 1 +
arch/powerpc/include/asm/barrier.h| 1 +
arch/powerpc/include/asm/bitops.h | 1 +
arch/powerpc/include/asm
Move all macros involving feature-fixups in a new file reg-ftr.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/exception-64s.h | 1 +
arch/powerpc/include/asm/reg-ftr.h | 63
arch/powerpc/include/asm/reg.h | 36 --
mmu-44x.h doesn't need asm/page.h if PAGE_SHIFT are replaced by
CONFIG_PPC_XX_PAGES
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mmu-44x.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-44x.h
b/arch/powerpc/include/as
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/pgtable.h | 4
arch/powerpc/include/asm/nohash/64/pgtable.h | 18 --
2 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h
b/arch/powerpc/include/as
Remove superflous includes and add missing ones
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/hw_breakpoint.h | 1 +
arch/powerpc/include/asm/processor.h | 5 ++---
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/hw_breakpoint.h
b/arch/
PPC_PIN_SIZE is specific to the 44x and is defined in mmu.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 5 -
arch/powerpc/include/asm/nohash/32/pgtable.h | 2 +-
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/book
set_breakpoint() is only used in process.c so make it static
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/debug.h | 1 -
arch/powerpc/kernel/process.c| 14 +++---
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/debug.h b/arch/p
Files not using fixmap consts or functions don't need asm/fixmap.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/fixmap.h| 2 --
arch/powerpc/kernel/head_8xx.S | 1 -
arch/powerpc/mm/dump_hashpagetable.c | 1 -
arch/powerpc/sysdev/cpm_common.c | 1 -
4 files changed,
files not using feature fixup don't need asm/feature-fixups.h
files using feature fixup need asm/feature-fixups.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/cputable.h| 1 -
arch/powerpc/include/asm/dbell.h | 1 +
arch/powerpc/include/asm/dt_cpu_ftrs.h
Only include linux/stringify.h is files using __stringify()
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/dcr-native.h| 1 +
arch/powerpc/include/asm/ppc-opcode.h| 1 -
arch/powerpc/include/asm/reg_fsl_emb.h | 2 ++
arch/powerpc/include/asm/synch.h
This patch moves ASM_CONST() and stringify_in_c() into
dedicated asm-const.h, then cleans all related inclusions.
Signed-off-by: Christophe Leroy
---
arch/powerpc/crypto/md5-asm.S | 1 +
arch/powerpc/crypto/sha1-powerpc-asm.S | 1 +
arch/powerpc/include/asm/asm-compat.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/asm-405.h | 19 +++
arch/powerpc/include/asm/asm-compat.h| 13 -
arch/powerpc/include/asm/atomic.h| 1 +
arch/powerpc/include/asm/bitops.h| 1 +
arch/powerpc/includ
Files not using cpu_has_feature() don't need cpu_has_feature.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/cacheflush.h | 1 -
arch/powerpc/include/asm/cputime.h| 1 -
arch/powerpc/include/asm/dbell.h | 1 -
arch/powerpc/kernel/vdso.c| 1 -
4 files changed,
page.h doesn't need kdump.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/page.h | 1 -
arch/powerpc/kernel/crash.c | 1 -
arch/powerpc/kernel/machine_kexec.c | 1 +
arch/powerpc/kernel/setup_32.c | 1 +
4 files changed, 2 insertions(+), 2 deletions(-)
diff --git
The purpose of this serie is to limit the number of includes to
only the necessary ones in order to reduce the number of files
recompiled everytime a header file is modified.
This is the start of the work, please provide feedback if any so
that I don't go in the wrong direction.
Handled inclusion
Latest GCC version emit the following warnings
As arch/powerpc code is built with -Werror, this breaks build with
GCC 8.1
This patch inhibits those warnings
CC arch/powerpc/kernel/syscalls.o
In file included from arch/powerpc/kernel/syscalls.c:24:
./include/linux/syscalls.h:233:18: error:
Sam Bobroff writes:
> As EEH event handling progresses, a cumulative result of type
> pci_ers_result is built up by (some of) the eeh_report_*() functions
> using either:
> if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
> if (*res == PCI_ERS_RESULT_NONE) *res = rc;
> or:
> if (
On 6/1/2018 1:40 PM, Michael Ellerman wrote:
> Scott Wood writes:
>
>> On Thu, 2018-05-31 at 14:35 +, Diana Madalina Craciun wrote:
>>> On 5/31/2018 5:21 PM, Michael Ellerman wrote:
We can add a nospectre_v1 command line option if necessary.
>>> What about nobarrier_nospec (or similar) in
Masahiro Yamada writes:
> 2018-06-01 19:34 GMT+09:00 Michael Ellerman :
...
>
> Could you update your branch, please?
Done.
I've only pushed the first three patches this time, to avoid any
confusion. Hopefully :)
The top commit is:
1421dc6d4829 ("powerpc/kbuild: Use flags variables rather th
Nicholas Piggin writes:
> On Fri, 01 Jun 2018 00:22:21 +1000
> Michael Ellerman wrote:
>> Nicholas Piggin writes:
>> > The stores to update the SLB shadow area must be made as they appear
>> > in the C code, so that the hypervisor does not see an entry with
>> > mismatched vsid and esid. Use WRI
Hi.
2018-06-01 19:34 GMT+09:00 Michael Ellerman :
> Hi Masahiro,
>
> Masahiro Yamada writes:
> ...
>>
>> Also, the change logs could be dropped.
>>
>> I see
>>
>> Since v1: reworded changelog to explain the cause of the problem (thanks
>> Segher) and moved the flags into the 64-32 cross compile c
Scott Wood writes:
> On Thu, 2018-05-31 at 14:35 +, Diana Madalina Craciun wrote:
>> On 5/31/2018 5:21 PM, Michael Ellerman wrote:
>> >
>> > We can add a nospectre_v1 command line option if necessary.
>>
>> What about nobarrier_nospec (or similar) instead of nospectre_v1 command
>> line? We
Hi Masahiro,
Masahiro Yamada writes:
...
>
> Also, the change logs could be dropped.
>
> I see
>
> Since v1: reworded changelog to explain the cause of the problem (thanks
> Segher) and moved the flags into the 64-32 cross compile case.
>
> or
>
> Since v1: removed extra -EB in the recordmcount s
When a single-threaded process has a non-local mm_cpumask, try to use
that point to flush the TLBs out of other CPUs in the cpumask.
An IPI is used for clearing remote CPUs for a few reasons:
- An IPI can end lazy TLB use of the mm, which is required to prevent
TLB entries being created on the r
Implementing pte_update with pte_xchg (which uses cmpxchg) is
inefficient. A single larx/stcx. works fine, no need for the less
efficient cmpxchg sequence.
Then remove the memory barriers from the operation. There is a
requirement for TLB flushing to load mm_cpumask after the store
that reduces pt
The ISA suggests ptesync after setting a pte, to prevent a table walk
initiated by a subsequent access from missing that store and causing a
spurious fault. This is an architectual allowance that allows an
implementation's page table walker to be incoherent with the store
queue.
However there is n
Prefetch the faulting address in update_mmu_cache to give the page
table walker perhaps 100 cycles head start as locks are dropped and
the interrupt completed.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/mm/mem.c | 4 +++-
arch/powerpc/mm/pgtable-book3s64.c | 3 ++-
2 files chan
This matches other architectures, when we know there will be no
further accesses to the address (e.g., for teardown), page table
entries can be cleared non-atomically.
The comments about NMMU are bogus: all MMU notifiers (including NMMU)
are released at this point, with their TLBs flushed. An NMMU
In the case of a spurious fault (which can happen due to a race with
another thread that changes the page table), the default Linux mm code
calls flush_tlb_page for that address. This is not required because
the pte will be re-fetched. Hash does not wire this up to a hardware
TLB flush for this rea
Radix flushes the TLB when updating ptes to increase permissiveness
of protection (increase access authority). Book3S does not require
TLB flushing in this case, and it is not done on hash. This patch
avoids the flush for radix.
>From Power ISA v3.0B, p.1090:
Setting a Reference or Change Bit
Since last time:
- Rebased on top of Aneesh's series "[PATCH V2 1/4] powerpc/mm/hugetlb:
Update huge_ptep_set_access_flags to call __ptep_set_access_flags"
Thanks,
Nick
Nicholas Piggin (7):
powerpc/64s/radix: do not flush TLB when relaxing access
powerpc/64s/radix: do not flush TLB on spuri
With split pmd page table lock enabled, we don't use mm->page_table_lock when
updating pmd entries. This patch update hugetlb path to use the right lock
when inserting huge page directory entries into page table.
ex: if we are using hugepd and inserting hugepd entry at the pmd level, we
use pmd_lo
When inserting SLB entries for EA above 512TB, we need to hard disable irq.
This will make sure we don't take a PMU interrupt that can possibly touch
user space address via a stack dump. To prevent this, we need to hard disable
the interrupt.
Also add a comment explaining why we don't need context
These are found in POWER9 chips. Right now these PHBs have unknown type
so changing it to PHB4 won't make much of a difference except enabling
sketchy bypass for POWER9 as this does below.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci.h | 1 +
arch/powerpc/platf
The existing sketchy bypass ignores the existing default 32bit TCE table
(created by default for every PE at boot time or after being used by
VFIO) and it allocates another table instead without updating PE DMA
config (pe->table_group). So if we decide to use such device for VFIO
later, this new ta
I came across this adhoc implementation and thought it could use some
polishing. This fixes memory leaks and add P9 support. Based on the current
upstream.
Please comment. Thanks.
Alexey Kardashevskiy (2):
powerpc/powernv: Reuse existing TCE code for sketchy bypass
powerpc/powernv: Define
We use PHB in mode1 which uses bit 59 to select a correct DMA window.
However there is mode2 which uses bits 59:55 and allows up to 32 DMA
windows per a PE.
Even though documentation does not clearly specify that, it seems that
the actual hardware does not support bits 59:55 even in mode1, in othe
Haren Myneni writes:
> NX increments readOffset by FIFO size in receive FIFO control register
> when CRB is read. But the index in RxFIFO has to match with the
> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
> may be processing incorrect CRBs and can cause CRB timeout.
>
>
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