In order to make generic IOV code work, the physical function IOV BAR
should start from offset of the first VF. Since M64 segments share
PE number space across PHB, and some PEs may be in use at the time
when IOV is enabled, the existing code shifts the IOV BAR to the index
of the first PE/VF. This
On 27/09/17 16:09, Alexey Kardashevskiy wrote:
> In order to make generic IOV code work, the physical function IOV BAR
> should start from offset of the first VF. Since M64 segments share
> PE number space across PHB, and some PEs may be in use at the time
> when IOV is enabled, the existing code s
Santosh Sivaraj writes:
> * Sergey Senozhatsky wrote (on 2017-09-20
> 16:29:02 +):
>
>> Hello
>>
>> RFC
>>
>> On some arches C function pointers are indirect and point to
>> a function descriptor, which contains the actual pointer to the code.
>> This mostly doesn'
In order to make generic IOV code work, the physical function IOV BAR
should start from offset of the first VF. Since M64 segments share
PE number space across PHB, and some PEs may be in use at the time
when IOV is enabled, the existing code shifts the IOV BAR to the index
of the first PE/VF. This
This code is used at boot and machine checks, so it should be using
early_radix_enabled() (which is usable any time).
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/mce_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powe
On Wed, 27 Sep 2017 12:55:51 +0800
Jeremy Kerr wrote:
> Commit 41d0c2ecde introduced calls to __flush_tlb_power[89] from the
> cpufeatures code, specifying the number of sets to flush.
>
> However, these functions take an action argument, not a number of sets.
> This means we hit the BUG() in __
Sergey Senozhatsky writes:
> On (09/22/17 16:48), Luck, Tony wrote:
> [..]
>> Tested patch series on ia64 successfully.
>>
>> Tested-by: Tony Luck
>
> thanks!
>
>> After this goes upstream, you should submit a patch to get rid of
>> all uses of %pF (70 instances in 35 files) and %pf (63 in 34)
Commit 41d0c2ecde introduced calls to __flush_tlb_power[89] from the
cpufeatures code, specifying the number of sets to flush.
However, these functions take an action argument, not a number of sets.
This means we hit the BUG() in __flush_tlb_{206,300} when using
cpufeatures-style configuration.
T
Hi Bjorn,
Yes, this works:
Tested-by: Daniel Axtens # arm64, ppc64-qemu-tcg
Regards,
Daniel
> On Fri, Sep 01, 2017 at 05:27:41PM +1000, Daniel Axtens wrote:
>> This patch set:
>>
>> - splits the default display handling out from VGA arbiter, into its
>>own file and behind its own Kconfig
Segher Boessenkool writes:
> On Tue, Sep 26, 2017 at 03:34:36PM +1000, Michael Ellerman wrote:
>> Cyril Bur writes:
>> > This was written for userspace which doesn't have to explicitly enable
>> > VMX in order to use it - we need to be smarter in the kernel.
>>
>> Well the kernel has to do it f
Paul Mackerras writes:
> On Tue, Sep 26, 2017 at 03:24:05PM +1000, Michael Ellerman wrote:
>> David Gibson writes:
>>
>> > On Fri, Sep 22, 2017 at 11:34:29AM +0200, Greg Kurz wrote:
>> >> Userland passes an array of 64 SLB descriptors to KVM_SET_SREGS,
>> >> some of which are valid (ie, SLB_ESI
From: Frederic Barrat
commit 197267d0356004a31c4d6b6336598f5dff3301e1 upstream.
cxl keeps a driver use count, which is used with the hash memory model
on p8 to know when to upgrade local TLBIs to global and to trigger
callbacks to manage the MMU for PSL8.
If a process opens a context and closes
From: Frederic Barrat
commit 197267d0356004a31c4d6b6336598f5dff3301e1 upstream.
cxl keeps a driver use count, which is used with the hash memory model
on p8 to know when to upgrade local TLBIs to global and to trigger
callbacks to manage the MMU for PSL8.
If a process opens a context and closes
- On Sep 26, 2017, at 1:51 PM, Mathieu Desnoyers
mathieu.desnoy...@efficios.com wrote:
> Provide a new command allowing processes to register their intent to use
> the private expedited command.
>
I missed a few maintainers that should have been CC'd. Adding them now.
This patch is aimed to
On Tuesday, September 26, 2017 9:25:30 PM CEST Christophe LEROY wrote:
>
> Le 26/09/2017 à 21:03, Christian Lamparter a écrit :
> > The mmu context on the 40x, 44x does not define pte_frag
> > entry. This causes gcc abort the compilation due to:
> >
> > setup-common.c: In function ‘setup_arch’:
>
Le 26/09/2017 à 21:03, Christian Lamparter a écrit :
The mmu context on the 40x, 44x does not define pte_frag
entry. This causes gcc abort the compilation due to:
setup-common.c: In function ‘setup_arch’:
setup-common.c:908: error: ‘mm_context_t’ has no ‘pte_frag’
This patch fixes the issue b
The mmu context on the 40x, 44x does not define pte_frag
entry. This causes gcc abort the compilation due to:
setup-common.c: In function ‘setup_arch’:
setup-common.c:908: error: ‘mm_context_t’ has no ‘pte_frag’
This patch fixes the issue by adding additional guard
conditions, that limit the init
On Wed, Sep 06, 2017 at 01:21:22AM +0200, Jan H. Schönherr wrote:
> The reset argument passed to pci_iov_add_virtfn() and
> pci_iov_remove_virtfn() is always zero since commit 46cb7b1bd86fc227a
> ("PCI: Remove unused SR-IOV VF Migration support").
>
> Remove the argument together with the associat
Hi,
On 15/09/2017 at 09:13:26 +0200, Anatolij Gustschin wrote:
> On Fri, 15 Sep 2017 04:00:04 +0200
> Alexandre Belloni alexandre.bell...@free-electrons.com wrote:
>
> >The proper compatible for rv3029 is microcrystal,rv3029.
> >
> >Signed-off-by: Alexandre Belloni
>
> Acked-by: Anatolij Gustsc
On Fri, 2017-09-22 at 03:32:21 UTC, Michael Neuling wrote:
> On POWER9 DD2.1 and below, it's possible for a paste instruction to
> cause a Machine Check Exception (MCE) where only DSISR bit 33 is
> set. This will result in the MCE handler seeing an unknown event,
> which triggers linux to crash.
>
On Tue, Sep 26, 2017 at 03:24:05PM +1000, Michael Ellerman wrote:
> David Gibson writes:
>
> > On Fri, Sep 22, 2017 at 11:34:29AM +0200, Greg Kurz wrote:
> >> Userland passes an array of 64 SLB descriptors to KVM_SET_SREGS,
> >> some of which are valid (ie, SLB_ESID_V is set) and the rest are
> >
On Tue, Sep 26, 2017 at 03:34:36PM +1000, Michael Ellerman wrote:
> Cyril Bur writes:
> > This was written for userspace which doesn't have to explicitly enable
> > VMX in order to use it - we need to be smarter in the kernel.
>
> Well the kernel has to do it for them after a trap, which is actua
There are two types of memory reservations firmware can ask the kernel
to make in the device tree: static and dynamic.
See Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
If you have greater than 16 entries in /reserved-memory (as we do on
POWER9 systems) you would get this s
Rob Herring writes:
> On Thu, Sep 14, 2017 at 5:24 AM, Stewart Smith
> wrote:
>> There are two types of memory reservations firmware can ask the kernel
>> to make in the device tree: static and dynamic.
>> See Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
>>
>> If you have
Hi Alexei,
Le 25/09/2017 à 18:27, Alexei Starovoitov a écrit :
On Mon, Sep 18, 2017 at 12:15 AM, Laurent Dufour
wrote:
Despite the unprovable lockdep warning raised by Sergey, I didn't get any
feedback on this series.
Is there a chance to get it moved upstream ?
what is the status ?
As me
Le 26/09/2017 à 03:44, Vaibhav Jain a écrit :
Hi Christophe,
A minor nitpick
Christophe Lombard writes:
+ for (dar = (addr & ~(page_size - 1)); dar < (addr + size); dar +=
page_size) {
+ if (dar < vma->vm_start || dar > vma->vm_end) {
Code comment in mm_types.h for vm_e
The in-kernel 'library' API can be called by drivers to help
interaction with an IBM XSL on a POWER9 system.
The cxllib_handle_fault() API is used to handle memory fault. All memory
pages of the specified buffer have to be handled but under certain
conditions,the last page may not be touched, and
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