Re: [PATCH v2 3/5] powerpc/mce: Hookup derror (load/store) UE errors

2017-09-12 Thread Balbir Singh
On Wed, Sep 13, 2017 at 4:21 PM, Nicholas Piggin wrote: > On Wed, 13 Sep 2017 16:10:47 +1000 > Balbir Singh wrote: > >> Extract physical_address for UE errors by walking the page >> tables for the mm and address at the NIP, to extract the >> instruction. Then use the instruction to find the effec

Re: [PATCH v2 3/5] powerpc/mce: Hookup derror (load/store) UE errors

2017-09-12 Thread Nicholas Piggin
On Wed, 13 Sep 2017 16:10:47 +1000 Balbir Singh wrote: > Extract physical_address for UE errors by walking the page > tables for the mm and address at the NIP, to extract the > instruction. Then use the instruction to find the effective > address via analyse_instr(). > > We might have page table

[PATCH v2 5/5] powerpc/mce: hookup memory_failure for UE errors

2017-09-12 Thread Balbir Singh
If we are in user space and hit a UE error, we now have the basic infrastructure to walk the page tables and find out the effective address that was accessed, since the DAR is not valid. We use a work_queue content to hookup the bad pfn, any other context causes problems, since memory_failure itse

[PATCH v2 4/5] powerpc/mce: Hookup ierror (instruction) UE errors

2017-09-12 Thread Balbir Singh
Hookup instruction errors (UE) for memory offling via memory_failure() in a manner similar to load/store errors (derror). Since we have access to the NIP, the conversion is a one step process in this case. Signed-off-by: Balbir Singh --- arch/powerpc/kernel/mce_power.c | 23 -

[PATCH v2 3/5] powerpc/mce: Hookup derror (load/store) UE errors

2017-09-12 Thread Balbir Singh
Extract physical_address for UE errors by walking the page tables for the mm and address at the NIP, to extract the instruction. Then use the instruction to find the effective address via analyse_instr(). We might have page table walking races, but we expect them to be rare, the physical address e

[PATCH v2 2/5] powerpc/mce: align the print of physical address better

2017-09-12 Thread Balbir Singh
Use the same alignment as Effective address and rename phyiscal address to Page Frame Number Signed-off-by: Balbir Singh --- arch/powerpc/kernel/mce.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c index e254399..f351adf

[PATCH v2 1/5] powerpc/mce.c: Remove unused function get_mce_fault_addr()

2017-09-12 Thread Balbir Singh
There are no users of get_mce_fault_addr() Fixes: b63a0ff ("powerpc/powernv: Machine check exception handling.") Signed-off-by: Balbir Singh --- arch/powerpc/include/asm/mce.h | 2 -- arch/powerpc/kernel/mce.c | 39 --- 2 files changed, 41 deletions(-)

[PATCH v2 0/4] Revisit MCE handling for UE Errors

2017-09-12 Thread Balbir Singh
This patch series is designed to hook up memory_failure on UE errors, this is specially helpful for user_mode UE errors. The first two patches cleanup bits, remove dead code. I could not find any users of get_mce_fault_addr(). The second one improves printing of physical address The third patch w

Re: [linux-next] [bisected a4615d11] Memory DLPAR triggers WARN_ONCE() in mm/page_vma_mapped.c

2017-09-12 Thread abdul
On Mon, 2017-09-11 at 10:53 -0400, Zi Yan wrote: > Hi Abdul, > > Can you try this patch below? I think I missed that pmd entries > can be zapped, so the WARN_ONCE is unnecessary. > > Thanks. > > diff --git a/mm/page_vma_mapped.c b/mm/page_vma_mapped.c > index 6a03946469a9..eb462e7db0a9 100644 >

[PATCH] powerpc: Fix handling of alignment interrupt on dcbz instruction

2017-09-12 Thread Paul Mackerras
This fixes the emulation of the dcbz instruction in the alignment interrupt handler. The error was that we were comparing just the instruction type field of op.type rather than the whole thing, and therefore the comparison "type != CACHEOP + DCBZ" was always true. Fixes: 31bfdb036f12 ("powerpc: U

Re: [PATCH v3 1/2] powerpc/mm: Export flush_all_mm()

2017-09-12 Thread Alistair Popple
> +static inline void hash__local_flush_all_mm(struct mm_struct *mm) > +{ > + /* > + * There's no Page Walk Cache for hash, so what is needed is > + * the same as flush_tlb_mm(), which doesn't really make sense > + * with hash. So the only thing we could do is flush the > +

Re: [PATCH v3 2/2] cxl: Enable global TLBIs for cxl contexts

2017-09-12 Thread Alistair Popple
I have tested the non-cxl specific parts (mm_context_add_copro/mm_context_remove_copro) with this series - https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=1681 - and it works well for npu. Tested-by: Alistair Popple On Sun, 3 Sep 2017 08:15:13 PM Frederic Barrat wrote: > The PSL a

Re: [PATCH v3 2/2] cxl: Enable global TLBIs for cxl contexts

2017-09-12 Thread Alistair Popple
On Fri, 8 Sep 2017 04:56:24 PM Nicholas Piggin wrote: > On Sun, 3 Sep 2017 20:15:13 +0200 > Frederic Barrat wrote: > > > The PSL and nMMU need to see all TLB invalidations for the memory > > contexts used on the adapter. For the hash memory model, it is done by > > making all TLBIs global as soo

Re: [RFC PATCH 1/2] core: implement OPAL_SIGNAL_SYSTEM_RESET with POWER9 scoms

2017-09-12 Thread Benjamin Herrenschmidt
On Wed, 2017-09-13 at 02:05 +1000, Nicholas Piggin wrote: > This implements a way to raise system reset interrupts on other > cores. This has not yet been tested on DD2 or with deeper sleep > states. Reminds me, we need to workaround a bug with XSCOMs on P9 PSCOMs to core in the range 20010A80-20

[PATCH] powerpc/kernel: Add 'ibm,thread-groups' property for CPU allocation

2017-09-12 Thread Michael Bringmann
powerpc/kernel: Add logic to parse the new property 'ibm,thread-groups" when it is present. The content of this property explicitly defines the number of threads per core as well as the PowerPC 'threads_core_mask'. The design provides a common device-tree for both P9 normal core and P9 fused core

[PATCH V3 4/4] powerpc: Enable support for ibm,drc-info devtree property

2017-09-12 Thread Michael Bringmann
prom_init.c: Enable support for new DRC device tree property "ibm,drc-info" in initial handshake between the Linux kernel and the front end processor. Signed-off-by: Michael Bringmann --- arch/powerpc/kernel/prom_init.c |1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/kernel/p

[PATCH V3 3/4] hotplug/drc-info: Add code to search ibm,drc-info property

2017-09-12 Thread Michael Bringmann
rpadlpar_core.c: Provide parallel routines to search the older device- tree properties ("ibm,drc-indexes", "ibm,drc-names", "ibm,drc-types" and "ibm,drc-power-domains"), or the new property "ibm,drc-info". The interface to examine the DRC information is changed from a "get" function that returns v

Subject: [PATCH V3 2/4] pseries/drc-info: Search DRC properties for CPU indexes

2017-09-12 Thread Michael Bringmann
pseries/drc-info: Provide parallel routines to convert between drc_index and CPU numbers at runtime, using the older device-tree properties ("ibm,drc-indexes", "ibm,drc-names", "ibm,drc-types" and "ibm,drc-power-domains"), or the new property "ibm,drc-info". Signed-off-by: Michael Bringmann --- C

[PATCH V3 1/4] powerpc/firmware: Add definitions for new drc-info firmware feature

2017-09-12 Thread Michael Bringmann
Firmware Features: Define new bit flag representing the presence of new device tree property "ibm,drc-info". The flag is used to tell the front end processor when the Linux kernel supports the new properties, and by the front end processor to tell the Linux kernel that the new property is present

[PATCH V3 0/4] powerpc/devtree: Add support for 'ibm,drc-info' property

2017-09-12 Thread Michael Bringmann
Several properties in the DRC device tree format are replaced by more compact representations to allow, for example, for the encoding of vast amounts of memory, and or reduced duplication of information in related data structures. "ibm,drc-info": This property, when present, replaces the following

Re: [PATCH] ASoC: fsl_ssi: Override bit clock rate based on slot number

2017-09-12 Thread Nicolin Chen
On Tue, Sep 12, 2017 at 04:35:13PM +0200, Arnaud Mouiche wrote: > >- * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels > >- * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. > >+ * freq: Output BCLK frequency = samplerate * 32 (fixed) * slots (or > >channels) > > S

[patch V2 29/29] lockup_detector: Cleanup hotplug locking mess

2017-09-12 Thread Thomas Gleixner
All watchdog thread related functions are delegated to the smpboot thread infrastructure, which handles serialization against CPU hotplug correctly. The sysctl interface is completely decoupled from anything which requires CPU hotplug protection. No need to protect the sysctl writes against cpu h

[patch V2 22/29] lockup_detector: Make watchdog_nmi_reconfigure() two stage

2017-09-12 Thread Thomas Gleixner
Both the perf reconfiguration and the powerpc watchdog_nmi_reconfigure() need to be done in two steps. 1) Stop all NMIs 2) Read the new parameters and start NMIs Right now watchdog_nmi_reconfigure() is a combination of both. To allow a clean reconfiguration add a 'run' argument and spli

[RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs with OPAL_SIGNAL_SYSTEM_RESET

2017-09-12 Thread Nicholas Piggin
There are two complications. The first is that sreset from stop states come in with SRR1 set to do a powersave wakeup, with an sreset reason encoded. The second is that threads on the same core can't be signalled directly so we must designate a bounce CPU to reflect the IPI back. --- arch/powerpc

[RFC PATCH 1/2] core: implement OPAL_SIGNAL_SYSTEM_RESET with POWER9 scoms

2017-09-12 Thread Nicholas Piggin
This implements a way to raise system reset interrupts on other cores. This has not yet been tested on DD2 or with deeper sleep states. --- core/Makefile.inc | 1 + core/sreset.c | 237 hw/xscom.c | 2 + include/skib

[RFC PATCH 0/2] NMI IPI work in progress for Linux and OPAL

2017-09-12 Thread Nicholas Piggin
Hi, I have Linux and OPAL patches that make the NMI IPI facility work on a POWER9 DD1 here, lightly tested. It works for threads that are running and are in stop (at least the stop0_lite state enabled in DD1). Comments on the OPAL patch in particular would be good. Next step will be more testing

[PATCH v8 6/6] powerpc/fadump: use the new parse_args callback arguments

2017-09-12 Thread Michal Suchanek
Signed-off-by: Michal Suchanek --- arch/powerpc/kernel/fadump.c | 47 1 file changed, 13 insertions(+), 34 deletions(-) diff --git a/arch/powerpc/kernel/fadump.c b/arch/powerpc/kernel/fadump.c index 8778e1cc0380..1678d99ea835 100644 --- a/arch/powerpc

[PATCH v8 5/6] boot/param: add pointer to current and next argument to unknown parameter callback

2017-09-12 Thread Michal Suchanek
The fadump parameter processing re-does the logic of next_arg quote stripping to determine where the argument ends. Pass pointer to the current and next argument instead to make this more robust. Signed-off-by: Michal Suchanek --- rebase on master split off changes to fadump.c add pointer to curr

[PATCH v8 4/6] powerpc/fadump: update the dequoting logic to match lib/cmdline.c

2017-09-12 Thread Michal Suchanek
Signed-off-by: Michal Suchanek --- arch/powerpc/kernel/fadump.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/fadump.c b/arch/powerpc/kernel/fadump.c index 0e08f1a80af2..b214c1e333dd 100644 --- a/arch/powerpc/kernel/fadump.c +++ b/arch/powerpc/ker

[PATCH v8 3/6] lib/cmdline.c: Remove quotes symmetrically.

2017-09-12 Thread Michal Suchanek
Remove quotes from argument value only if there is qoute on both sides. Signed-off-by: Michal Suchanek --- lib/cmdline.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/lib/cmdline.c b/lib/cmdline.c index 171c19b6888e..6d398a8b63fc 100644 --- a/lib/cmdline.c +++ b/

[PATCH v8 2/6] powerpc/fadump: update documentation about 'fadump_extra_args=' parameter

2017-09-12 Thread Michal Suchanek
With the introduction of 'fadump_extra_args=' parameter to pass additional parameters to fadump (capture) kernel, update documentation about it. Signed-off-by: Hari Bathini Signed-off-by: Michal Suchanek --- Documentation/powerpc/firmware-assisted-dump.txt | 20 +++- 1 file chan

[PATCH v8 1/6] powerpc/fadump: reduce memory consumption for capture kernel

2017-09-12 Thread Michal Suchanek
With fadump (dump capture) kernel booting like a regular kernel, it needs almost the same amount of memory to boot as the production kernel, which is unwarranted for a dump capture kernel. But with no option to disable some of the unnecessary subsystems in fadump kernel, that much memory is wasted

Re: [PATCH] ASoC: fsl_ssi: Override bit clock rate based on slot number

2017-09-12 Thread Arnaud Mouiche
Hello Nicolin On 08/09/2017 07:23, Nicolin Chen wrote: The set_sysclk() now is used to override the output bit clock rate. But this is not a common way to implement a set_dai_sysclk(). And this creates a problem when a general machine driver (simple-card for example) tries to do set_dai_sysclk()

Re: [PATCH v2 3/9] powerpc/powernv: Remove real mode access limit for early allocations

2017-09-12 Thread Benjamin Herrenschmidt
On Tue, 2017-09-12 at 15:43 +0530, Aneesh Kumar K.V wrote: > Yes. I added the limit to radix after I observed that we have MSR[SF] = > 0. > > IIRC it was PACA access that was causing it to crash on return from RTAS. > > hmm the commit also explains that. > > powerpc/mm/radix: Limit paca allocati

Re: [PATCH v2 3/9] powerpc/powernv: Remove real mode access limit for early allocations

2017-09-12 Thread Aneesh Kumar K.V
Benjamin Herrenschmidt writes: > On Mon, 2017-08-14 at 22:49 +1000, Michael Ellerman wrote: >> > - /* >> > - * We limit the allocation that depend on ppc64_rma_size >> > - * to first_memblock_size. We also clamp it to 1GB to >> > - * avoid some funky things such as RTAS bugs. >

[PATCH] crypto: talitos - Don't provide setkey for non hmac hashing algs.

2017-09-12 Thread Christophe Leroy
Today, md5sum fails with error -ENOKEY because a setkey function is set for non hmac hashing algs, see strace output below: mmap(NULL, 378880, PROT_READ, MAP_SHARED, 6, 0) = 0x77f5 accept(3, 0, NULL) = 7 vmsplice(5, [{"bin/\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\

Re: [PATCH v1 0/4] Revisit MCE handling for UE Errors

2017-09-12 Thread Balbir Singh
On Tue, Sep 12, 2017 at 3:03 PM, Nicholas Piggin wrote: > Hi Balbir, > > Very cool. How are you testing it? Is it failing memory pages > and poisoning them out properly? > Yep, I tested it and it seems to work correctly so far. I am testing this on a simulator with injected MCE UE errors for both