Nicholas Piggin writes:
> Current busy-wait loops are implemented by repeatedly calling cpu_relax()
> to give an arch option for a low-latency option to improve power and/or
> SMT resource contention.
>
> This poses some difficulties for powerpc, which has SMT priority setting
> instructions (pri
From: Ian Munsie
I am no longer employed by IBM and will no longer have access to cxl
hardware, so remove myself as a cxl maintainer.
If anyone needs to contact me in the future, please use my personal
email address darkstarsw...@gmail.com
Signed-off-by: Ian Munsie
Cc: Frederic Barrat
Cc: And
We can use pfn_to_page in realmode for other configs. Hence remove the
CONFIG_FLATMEM ifdef
Fixes: 8e0861fa3c4ed (powerpc: Prepare to support kernel handling of IOMMU
map/unmap)
Cc: Alexey Kardashevskiy
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/init_64.c | 2 +-
1 file changed, 1 in
Benjamin Herrenschmidt writes:
> That will allow OPAL to configure the CPU in an optimal way.
>
> Signed-off-by: Benjamin Herrenschmidt
> ---
>
> The matching OPAL change has been sent to the skiboot list.
>
> Setting those bits in the reinit() call with an older OPAL
> will result in the call r
On Wed, 28 Jun 2017 06:46:49 +0530
Akshay Adiga wrote:
> pnv_wakeup_noloss expects R12 to contain SRR1 value to determine if
> the wakeup reason is an HMI in CHECK_HMI_INTERRUPT.
>
> When we wakeup with ESL=0, SRR1 will not contain the wakeup reason, so
> there is no point setting R12 to SRR1.
>
On Wed, 28 Jun 2017 08:21:55 +0530
"Aneesh Kumar K.V" wrote:
> Nicholas Piggin writes:
>
> > There are two cases outside the normal address space management
> > where a CPU's local TLB is to be flushed:
> >
> > 1. Host boot; in case something has left stale entries in the
> > TLB (e.g.,
Nicholas Piggin writes:
> There are two cases outside the normal address space management
> where a CPU's local TLB is to be flushed:
>
> 1. Host boot; in case something has left stale entries in the
> TLB (e.g., kexec).
>
> 2. Machine check; to clean corrupted TLB entries.
>
> CPU state
Ram Pai writes:
> Display the pkey number associated with the vma in smaps of a task.
> The key will be seen as below:
>
> VmFlags: rd wr mr mw me dw ac key=0
Why wouldn't we just emit a "ProtectionKey:" line like x86 does?
See their arch_show_smap().
You should probably also do what x86 does,
Greg Kroah-Hartman writes:
> On Thu, Jun 22, 2017 at 04:52:51PM +1000, Michael Ellerman wrote:
>> The SLB miss handler calls slb_allocate_realmode() in order to create an
>> SLB entry for the faulting address. At the very start of that function
>> we check that the faulting Effective Address (EA)
Flip the switch. Running around and screaming "IT'S ALIVE" is optional,
but recommended.
Signed-off-by: Oliver O'Halloran
---
v3: Only select when building for 64bit Book3-S
---
arch/powerpc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
i
From: Anton Blanchard
Adds support for removing bolted (i.e kernel linear mapping) mappings on
powernv. This is needed to support memory hot unplug operations which
are required for the teardown of DAX/PMEM devices.
Reviewed-by: Balbir Singh
Reviewed-by: Rashmica Gupta
Signed-off-by: Anton Bla
Add support for the devmap bit on PTEs and PMDs for PPC64 Book3S. This
is used to differentiate device backed memory from transparent huge
pages since they are handled in more or less the same manner by the core
mm code.
Cc: Aneesh Kumar K.V
Signed-off-by: Oliver O'Halloran
---
v1 -> v2: Proper
Adds support to powerpc for the altmap feature of ZONE_DEVICE memory. An
altmap is a driver provided region that is used to provide the backing
storage for the struct pages of ZONE_DEVICE memory. In situations where
large amount of ZONE_DEVICE memory is being added to the system the
altmap reduces
Removes an indentation level and shuffles some code around to make the
following patch cleaner. No functional changes.
Reviewed-by: Balbir Singh
Signed-off-by: Oliver O'Halloran
---
v1 -> v2: Remove broken initialiser
---
arch/powerpc/mm/init_64.c | 48 --
Currently ZONE_DEVICE depends on X86_64 and this will get unwieldly as
new architectures (and platforms) get ZONE_DEVICE support. Move to an
arch selected Kconfig option to save us the trouble.
Cc: linux...@kvack.org
Acked-by: Ingo Molnar
Acked-by: Balbir Singh
Signed-off-by: Oliver O'Halloran
pnv_wakeup_noloss expects R12 to contain SRR1 value to determine if
the wakeup reason is an HMI in CHECK_HMI_INTERRUPT.
When we wakeup with ESL=0, SRR1 will not contain the wakeup reason, so
there is no point setting R12 to SRR1.
However, we don't set R12 at all and R12 contains garbage, and stil
On Fri, Apr 28, 2017 at 6:45 PM, Geliang Tang wrote:
> Use memdup_user() helper instead of open-coding to simplify the code.
>
> Signed-off-by: Geliang Tang
Thanks! Applied for -next.
-Kees
> ---
> arch/powerpc/kernel/nvram_64.c | 14 +-
> 1 file changed, 5 insertions(+), 9 deleti
On Mon, Jun 26, 2017 at 6:26 PM, Logan Gunthorpe wrote:
> Hi Jyri,
>
> Thanks for the ack. However, I'm reworking this patch set to use the
> include/linux/io-64-nonatomic* headers which will explicitly devolve
> into two 32-bit transfers. It's not clear whether this is appropriate
> for the tilcd
From: Madalin Bucur
Date: Mon, 26 Jun 2017 18:47:00 +0300
> A previous commit (5567e989198b5a8d) inserted a dependency on DMA
> API that requires HAS_DMA to be added in Kconfig.
>
> Signed-off-by: Madalin Bucur
Applied, thank you.
Le 27/06/2017 à 14:32, David Laight a écrit :
From: Frederic Barrat
Sent: 26 June 2017 19:09
P9 has support for PCI peer-to-peer, enabling a device to write in the
mmio space of another device directly, without interrupting the CPU.
This patch adds support for it on powernv, by adding a new A
> -Original Message-
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+leoli=freescale@lists.ozlabs.org] On Behalf Of David Laight
> Sent: Monday, June 26, 2017 10:55 AM
> To: 'Karim Eshapa' ; o...@buserror.net
> Cc: Roy Pledge ; linux-ker...@vger.kernel.org;
> Claudiu Manoil ; col
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Saturday, June 24, 2017 9:47 PM
> To: Karim Eshapa
> Cc: Roy Pledge ; linux-ker...@vger.kernel.org;
> Claudiu Manoil ; colin.k...@canonical.com;
> linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.or
Hello, Abdul.
Sorry about the long delay.
On Mon, Jun 12, 2017 at 04:53:42PM +0530, Abdul Haleem wrote:
> linux-next kernel crashed while running CPU offline and online.
>
> Machine: Power 8 LPAR
> Kernel : 4.12.0-rc4-next-20170609
> gcc : version 5.2.1
> config: attached
> testcase: CPU off/on
On Tuesday 27 June 2017 03:41 PM, Ram Pai wrote:
Pass the correct protection key value to the hash functions on
page fault.
Signed-off-by: Ram Pai
---
arch/powerpc/include/asm/pkeys.h | 11 +++
arch/powerpc/mm/hash_utils_64.c | 4
arch/powerpc/mm/mem.c| 6 +
mpsc.c and mpc52xx-psc.c are platform-specific serial drivers, and
should be compiled for the respective platforms only.
Signed-off-by: Hannes Reinecke
---
arch/powerpc/boot/Makefile | 7 ---
arch/powerpc/boot/serial.c | 4
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/
Hi Mark,
Thanks for the review and sorry, I really should have added more
context. I was originally just going to send this to the linux-nvdimm
list, but I figured the wider device-tree community might be
interested too.
Preamble:
Non-volatile DIMMs (nvdimms) are otherwise normal DDR DIMMs that
Thiago Jung Bauermann writes:
> Hello,
>
> The hypervisor interface to access 24x7 performance counters (which collect
> performance information from system power on to system power off) has been
> extended in POWER9 adding new fields to the request and result element
> structures.
>
> Also, resu
From: Frederic Barrat
> Sent: 26 June 2017 19:09
> P9 has support for PCI peer-to-peer, enabling a device to write in the
> mmio space of another device directly, without interrupting the CPU.
>
> This patch adds support for it on powernv, by adding a new API to be
> called by drivers. The pnv_pci
On Tue, 2017-06-20 at 08:37:28 UTC, Alistair Popple wrote:
> NPU2 requires an extra explicit flush to an active GPU PID when sending
> address translation shoot downs (ATSDs) to reliably flush the GPU TLB. This
> patch adds just such a flush at the end of each sequence of ATSDs.
>
> We can safely
On Tue, Jun 27, 2017 at 7:07 AM, Rafael J. Wysocki wrote:
> On Monday, June 26, 2017 01:34:52 PM Balbir Singh wrote:
>> On Sat, Jun 3, 2017 at 11:27 PM, Pavel Machek wrote:
>> > On Sat 2017-06-03 20:52:32, Balbir Singh wrote:
>> >> Kbuild reported a build failure when CONFIG_STRICT_KERNEL_RWX was
On Tue, 2017-06-27 at 03:11 -0700, Ram Pai wrote:
> Currently sys_pkey_create() provides the ability to disable read
> and write permission on the key, at creation. powerpc has the
> hardware support to disable execute on a pkey as well.This patch
> enhances the interface to let disable execute
On Tue, 2017-06-27 at 03:11 -0700, Ram Pai wrote:
> x86 does not support disabling execute permissions on a pkey.
>
> Signed-off-by: Ram Pai
> ---
> arch/x86/kernel/fpu/xstate.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate
On Tue, 2017-06-27 at 10:32 +0200, Christophe LEROY wrote:
>
> Le 27/06/2017 à 09:48, Balbir Singh a écrit :
> > This patch creates the window using text_poke_area, allocated
> > via get_vm_area(). text_poke_area is per CPU to avoid locking.
> > text_poke_area for each cpu is setup using late_init
On Tue, 2017-06-27 at 10:34 +0200, Christophe LEROY wrote:
>
> Le 27/06/2017 à 09:48, Balbir Singh a écrit :
> > With text moving to read-only migrate optprobes to using
> > the patch_instruction infrastructure. Without this optprobes
> > will fail and complain.
> >
> > Signed-off-by: Balbir Sing
This is a note to let you know that I've just added the patch titled
powerpc/slb: Force a full SLB flush when we insert for a bad EA
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch i
On Thu, Jun 22, 2017 at 04:52:51PM +1000, Michael Ellerman wrote:
> The SLB miss handler calls slb_allocate_realmode() in order to create an
> SLB entry for the faulting address. At the very start of that function
> we check that the faulting Effective Address (EA) is less than
> PGTABLE_RANGE (ign
This is a note to let you know that I've just added the patch titled
powerpc/slb: Force a full SLB flush when we insert for a bad EA
to the 3.18-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch
On Tue, 2017-06-27 at 03:11 -0700, Ram Pai wrote:
> Currently there are only 4bits in the vma flags to support 16 keys
> on x86. powerpc supports 32 keys, which needs 5bits. This patch
> introduces an addition bit in the vma flags.
>
> Signed-off-by: Ram Pai
> ---
> fs/proc/task_mmu.c | 6
On Tue, 2017-06-27 at 03:11 -0700, Ram Pai wrote:
> Memory protection keys enable applications to protect its
> address space from inadvertent access or corruption from
> itself.
>
> The overall idea:
>
> A process allocates a key and associates it with
> a address range withinits a
Hi,
On Tue, Jun 27, 2017 at 08:28:49PM +1000, Oliver O'Halloran wrote:
> A fairly bare-bones set of device-tree bindings so libnvdimm can be used
> on powerpc and other, less cool, device-tree based platforms.
;)
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Oliver O'Halloran
> ---
> The cu
Scan the devicetree for nonvolatile-memory buses and instantiate a
platform device for them.
Signed-off-by: Oliver O'Halloran
---
arch/powerpc/platforms/powernv/opal.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/platforms/powernv/opal.c
b/arch/powerpc/platforms/powernv/o
Adds powerpc64 implementations of:
memcpy_flushcache()
arch_wb_cache_pmem()
arch_invalidate_pmem()
Which form the architecture-specific portition of the persistent memory
API. These functions provide cache-management primitives for the DAX
drivers and libNVDIMM.
Signed-of
A fairly bare-bones set of device-tree bindings so libnvdimm can be used
on powerpc and other, less cool, device-tree based platforms.
Cc: devicet...@vger.kernel.org
Signed-off-by: Oliver O'Halloran
---
The current bindings are essentially this:
nonvolatile-memory {
compatible = "nonvola
struct device contains the ->of_node pointer so that devices can be
assoicated with the device-tree node that created them on DT platforms.
libnvdimm hides the struct device for regions and nvdimm devices inside
of an opaque structure so this patch adds accessors for each to allow
the of_nvdimm dri
Display the pkey number associated with the vma in smaps of a task.
The key will be seen as below:
VmFlags: rd wr mr mw me dw ac key=0
Signed-off-by: Ram Pai
---
Documentation/filesystems/proc.txt | 3 ++-
fs/proc/task_mmu.c | 22 +++---
2 files changed, 13 inse
Add documentation updates that capture PowerPC specific changes.
Signed-off-by: Ram Pai
---
Documentation/vm/protection-keys.txt | 89
1 file changed, 69 insertions(+), 20 deletions(-)
diff --git a/Documentation/vm/protection-keys.txt
b/Documentation/vm/pro
Since PowerPC and Intel both support memory protection keys, moving
the documenation to arch-neutral directory.
Signed-off-by: Ram Pai
---
Documentation/vm/protection-keys.txt | 85 +++
Documentation/x86/protection-keys.txt | 85 --
Abstracted out the arch specific code into the header file, and
added powerpc specific changes.
a) added 4k-backed hpte, memory allocator, powerpc specific.
b) added three test case where the key is associated after the page is
accessed/allocated/mapped.
c) cleaned up the code to make chec
Signed-off-by: Ram Pai
---
tools/testing/selftests/vm/Makefile |1 +
tools/testing/selftests/vm/pkey-helpers.h | 219
tools/testing/selftests/vm/protection_keys.c | 1395 +
tools/testing/selftests/x86/Makefile |2 +-
tools/testing/self
The value of the AMR register at the time of exception
is made available in gp_regs[PT_AMR] of the siginfo.
The value of the pkey, whose protection got violated,
is made available in si_pkey field of the siginfo structure.
Signed-off-by: Ram Pai
---
arch/powerpc/include/asm/paca.h| 1 +
Handle Data and Instruction exceptions caused by memory
protection-key.
Signed-off-by: Ram Pai
---
arch/powerpc/include/asm/mmu_context.h | 12 ++
arch/powerpc/include/asm/reg.h | 2 +-
arch/powerpc/mm/fault.c| 20 +
arch/powerpc/mm/pkeys.c| 7
Replace the magic number used to check for DSI exception
with a meaningful value.
Signed-off-by: Ram Pai
---
arch/powerpc/include/asm/reg.h | 7 ++-
arch/powerpc/kernel/exceptions-64s.S | 2 +-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.
Pass the correct protection key value to the hash functions on
page fault.
Signed-off-by: Ram Pai
---
arch/powerpc/include/asm/pkeys.h | 11 +++
arch/powerpc/mm/hash_utils_64.c | 4
arch/powerpc/mm/mem.c| 6 ++
3 files changed, 21 insertions(+)
diff --git a/arch/
Map the PTE protection key bits to the HPTE key protection bits,
while creating HPTE entries.
Signed-off-by: Ram Pai
---
Makefile | 2 +-
arch/powerpc/include/asm/book3s/64/mmu-hash.h | 5 +
arch/powerpc/include/asm/pkeys.h | 9 +
ar
Prepare the hash functions to be aware of protection keys.
This key will later be used to program the HPTE.
Signed-off-by: Ram Pai
---
arch/powerpc/include/asm/book3s/64/hash.h | 2 +-
arch/powerpc/include/asm/book3s/64/mmu-hash.h | 14 ++-
arch/powerpc/mm/hash64_4k.c
This system call, associates the pkey with vma corresponding to
the given address range.
Signed-off-by: Ram Pai
---
arch/powerpc/include/asm/mman.h| 8 ++-
arch/powerpc/include/asm/pkeys.h | 17 ++-
arch/powerpc/include/asm/systbl.h | 1 +
arch/powerpc/include/asm/unistd
Store and restore the AMR, IAMR and UMOR register state of the task
before scheduling out and after scheduling in, respectively.
Signed-off-by: Ram Pai
---
arch/powerpc/include/asm/processor.h | 5 +
arch/powerpc/kernel/process.c| 18 ++
2 files changed, 23 insertion
Sys_pkey_alloc() allocates and returns available pkey
Sys_pkey_free() frees up the pkey.
Total 32 keys are supported on powerpc. However pkey 0,1 and 31
are reserved. So effectively we have 29 pkeys.
Each key can be initialized to disable read, write and execute
permissions. On powerpc a key
x86 does not support disabling execute permissions on a pkey.
Signed-off-by: Ram Pai
---
arch/x86/kernel/fpu/xstate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index c24ac1e..d582631 100644
--- a/arch/x86/kernel/fpu/xstate.
Currently sys_pkey_create() provides the ability to disable read
and write permission on the key, at creation. powerpc has the
hardware support to disable execute on a pkey as well.This patch
enhances the interface to let disable execute at key creation
time. x86 does not allow this. Henc
Currently there are only 4bits in the vma flags to support 16 keys
on x86. powerpc supports 32 keys, which needs 5bits. This patch
introduces an addition bit in the vma flags.
Signed-off-by: Ram Pai
---
fs/proc/task_mmu.c | 6 +-
include/linux/mm.h | 18 +-
2 files changed,
Memory protection keys enable applications to protect its
address space from inadvertent access or corruption from
itself.
The overall idea:
A process allocates a key and associates it with
a address range withinits address space.
The process than can dynamically set read/wri
On Mon, 26 Jun 2017 16:06:00 +0200
Michal Suchanek wrote:
> When fadump is already registered return success.
>
> Currently EEXIST is returned which is difficult to handle race-free in
> userspace when shell scripts are used. If multiple writers are trying
> to write '1' there is no difference i
On 2017/04/27 11:21AM, Masami Hiramatsu wrote:
> On Thu, 27 Apr 2017 01:38:10 +0530
> "Naveen N. Rao" wrote:
>
> > Michael Ellerman wrote:
> > > "Naveen N. Rao" writes:
> > >> diff --git a/kernel/kallsyms.c b/kernel/kallsyms.c
> > >> index 6a3b249a2ae1..d134b060564f 100644
> > >> --- a/kernel/ka
Le 27/06/2017 à 09:48, Balbir Singh a écrit :
With text moving to read-only migrate optprobes to using
the patch_instruction infrastructure. Without this optprobes
will fail and complain.
Signed-off-by: Balbir Singh
Didn't Michael picked it up already ?
Christophe
---
arch/powerpc/ker
Le 27/06/2017 à 09:48, Balbir Singh a écrit :
arch_arm/disarm_probe use direct assignment for copying
instructions, replace them with patch_instruction
Signed-off-by: Balbir Singh
Didn't Michael picked it up already ?
Christophe
---
arch/powerpc/kernel/kprobes.c | 4 ++--
1 file chang
Le 27/06/2017 à 09:48, Balbir Singh a écrit :
This patch creates the window using text_poke_area, allocated
via get_vm_area(). text_poke_area is per CPU to avoid locking.
text_poke_area for each cpu is setup using late_initcall, prior
to setup of these alternate mapping areas, we continue to us
On Tue, Jun 27, 2017 at 12:33 PM, Michael Ellerman wrote:
> kbuild test robot writes:
>
>> Hi Oliver,
>>
>> [auto build test ERROR on powerpc/next]
>> [also build test ERROR on v4.12-rc6 next-20170623]
>> [if your patch is applied to the wrong git tree, please drop us a note to
>> help improve t
We have the basic support in the form of patching R/O
text sections, linker scripts for extending alignment
of text data. We've also got mark_rodata_ro()
NOTE: There is a temporary work-around for disabling
STRICT_KERNEL_RWX if CONFIG_HIBERNATION is enabled
Signed-off-by: Balbir Singh
---
arch/
The patch splits the linear page mapping such that
the ones with kernel text are mapped as 2M and others
are mapped with the largest possible size - 1G. The downside
of this is that we split a 1G mapping into 512 2M mappings
for the kernel, but in the absence of that we cannot support
R/O areas in
With hash we update the bolted pte to mark it read-only. We rely
on the MMU_FTR_KERNEL_RO to generate the correct permissions
for read-only text. The radix implementation just prints a warning
in this implementation
Signed-off-by: Balbir Singh
---
arch/powerpc/include/asm/book3s/64/hash.h | 3
PAPR has pp0 in bit 55, currently we assumed that bit
pp0 is bit 0 (all bits in IBM order). This patch fixes
the pp0 bits for both these routines that use H_PROTECT.
(e58e87a powerpc/mm: Update _PAGE_KERNEL_RO)
Signed-off-by: Balbir Singh
---
arch/powerpc/platforms/pseries/lpar.c | 21 +
For CONFIG_STRICT_KERNEL_RWX align __init_begin to 16M.
We use 16M since its the larger of 2M on radix and 16M
on hash for our linear mapping. The plan is to have
.text, .rodata and everything upto __init_begin marked
as RX. Note we still have executable read only data.
We could further align rodat
Move from mwrite() to patch_instruction() for xmon for
breakpoint addition and removal.
Signed-off-by: Balbir Singh
---
arch/powerpc/xmon/xmon.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index a728e19..08e367e 1
With text moving to read-only migrate optprobes to using
the patch_instruction infrastructure. Without this optprobes
will fail and complain.
Signed-off-by: Balbir Singh
---
arch/powerpc/kernel/optprobes.c | 58 ++---
1 file changed, 37 insertions(+), 21 delet
arch_arm/disarm_probe use direct assignment for copying
instructions, replace them with patch_instruction
Signed-off-by: Balbir Singh
---
arch/powerpc/kernel/kprobes.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kpro
This patch creates the window using text_poke_area, allocated
via get_vm_area(). text_poke_area is per CPU to avoid locking.
text_poke_area for each cpu is setup using late_initcall, prior
to setup of these alternate mapping areas, we continue to use
direct write to change/modify kernel text. With
Provide STRICT_KERNEL_RWX for PPC64/BOOK3S
These patches enable RX mappings of kernel text.
rodata is mapped RX as well as a trade-off, there
are more details in the patch description
As a prerequisite for R/O text, patch_instruction
is moved over to using a separate mapping that
allows write to
On Monday 19 June 2017 05:21 AM, Anton Blanchard wrote:
From: Anton Blanchard
Similar to POWER8, POWER9 can count run cycles and run instructions
completed on more than one PMU.
Acked-by: Madhavan Srinivasan
Signed-off-by: Anton Blanchard
---
arch/powerpc/perf/power9-events-list.h | 4
nr_cpu_ids can be limited by nr_cpus boot parameter, whereas NR_CPUS is a
compile time constant, which shouldn't be compared against during cpu kick.
Signed-off-by: Santosh Sivaraj
---
arch/powerpc/kernel/smp.c| 2 +-
arch/powerpc/platforms/cell/smp.c| 2 +-
arch/powerpc/platform
During secondary start, we do not need to BUG_ON if an invalid CPU number
is passed. We already print an error if secondary cannot be started, so
just return an error instead.
Signed-off-by: Santosh Sivaraj
---
arch/powerpc/kernel/smp.c| 3 ++-
arch/powerpc/platforms/cell/smp.c|
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