Le 29/05/2017 à 00:58, Balbir Singh a écrit :
On Sun, 2017-05-28 at 16:29 +0200, christophe leroy wrote:
Le 25/05/2017 à 05:36, Balbir Singh a écrit :
Today our patching happens via direct copy and
patch_instruction. The patching code is well
contained in the sense that copying bits are limi
Use the normal kernel crash path in more cases (whenever we're not
the init task), because it generally leads to much better Linux crash
information.
POWER9 has introduced more machine check conditions that can be
triggered by programming errors (as opposed to hardware errors),
which need to be de
The i-side 0111b case was missed by 7b9f71f974 ("powerpc/64s: POWER9
machine check handler").
It is possible to trigger this exception by branching to a foreign real
address (bits [8:12] != 0) with instruction relocation off, and verify
the exception cause is found after this patch.
Fixes: 7b9f71
Signed-off-by: Madalin Bucur
Signed-off-by: Camelia Groza
---
Documentation/networking/dpaa.txt | 194 ++
1 file changed, 194 insertions(+)
create mode 100644 Documentation/networking/dpaa.txt
diff --git a/Documentation/networking/dpaa.txt
b/Documentation/n
Le 29/05/2017 à 00:50, Balbir Singh a écrit :
On Sun, 2017-05-28 at 17:59 +0200, christophe leroy wrote:
Le 25/05/2017 à 05:36, Balbir Singh a écrit :
Today our patching happens via direct copy and
patch_instruction. The patching code is well
contained in the sense that copying bits are limi
Reza Arbab writes:
> On Fri, May 26, 2017 at 01:46:58PM +1000, Michael Ellerman wrote:
>>Reza Arbab writes:
>>
>>> On Thu, May 25, 2017 at 04:19:53PM +1000, Michael Ellerman wrote:
The commit message for 3af229f2071f says:
In practice, we never see a system with 256 NUMA nodes,
David Laight writes:
> From: Michael Ellerman
>> Sent: 26 May 2017 08:24
>> Nicholas Piggin writes:
>> > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
>> > index f11f65634aab..438fdb0fb142 100644
>> > --- a/arch/powerpc/xmon/xmon.c
>> > +++ b/arch/powerpc/xmon/xmon.c
>> > @@
Rob Landley writes:
> On 05/25/2017 04:24 PM, Stephen Rothwell wrote:
>> Hi Michael,
>>
>> On Thu, 25 May 2017 23:02:06 +1000 Michael Ellerman
>> wrote:
>>>
>>> It'll be:
>>>
>>> ee35011fd032 ("initramfs: make initramfs honor CONFIG_DEVTMPFS_MOUNT")
>>
>> And Andrew has asked me to drop that p
OCC provides historical minimum and maximum value for the sensor
readings. This patch exports them as highest and lowest attributes
for the inband sensors copied by OCC to main memory.
Signed-off-by: Shilpasri G Bhat
---
Changes from V4:
- Got rid of 'len' variable in populate_attr_groups
drive
Current busy-wait loops are implemented by repeatedly calling cpu_relax()
to give an arch option for a low-latency option to improve power and/or
SMT resource contention.
This poses some difficulties for powerpc, which has SMT priority setting
instructions (priorities determine how ifetch cycles a
We are running low on CPU feature bits, so we only want to use them when
it's really necessary.
CPU_FTR_SUBCORE is only used in one place, and only in C, so we don't
need it in order to make asm patching work. It can only be set on
"Power8" CPUs, which in practice means POWER8, POWER8E and POWER8N
POWER9 introduces a new mode for the decrementer register, called
large decrementer mode, in which the decrementer counter is 56 bits
wide rather than 32, and reads are sign-extended rather than
zero-extended.
Since KVM code reads and writes the host decrementer value in a few
places, it needs to
One of the new features of POWER9 is that the decrementer (the
facility that provides an interrupt after a programmable length of
time) has been increased in size from 32 bits to 56 bits, allowing
time intervals of up to about 814 days, compared to 4 seconds
previously. This patch series adds supp
This allows userspace (e.g. QEMU) to enable large decrementer mode
for the guest, by setting the LPCR_LD bit in the guest LPCR value.
With this, the guest exit code saves 64 bits of the guest DEC value
on exit. Other places that use the guest DEC value check the LPCR_LD
bit in the guest LPCR value
On Sun, 2017-05-28 at 16:29 +0200, christophe leroy wrote:
>
> Le 25/05/2017 à 05:36, Balbir Singh a écrit :
> > Today our patching happens via direct copy and
> > patch_instruction. The patching code is well
> > contained in the sense that copying bits are limited.
> >
> > While considering impl
On Sun, 2017-05-28 at 17:59 +0200, christophe leroy wrote:
>
> Le 25/05/2017 à 05:36, Balbir Singh a écrit :
> > Today our patching happens via direct copy and
> > patch_instruction. The patching code is well
> > contained in the sense that copying bits are limited.
> >
> > While considering impl
On Sun, 2017-05-28 at 20:00 +0200, christophe leroy wrote:
>
> Le 25/05/2017 à 05:36, Balbir Singh a écrit :
> > Today our patching happens via direct copy and
> > patch_instruction. The patching code is well
> > contained in the sense that copying bits are limited.
> >
> > While considering impl
On Sun, 2017-05-28 at 11:47 +0200, Michal Suchanek wrote:
> On Tue, 9 May 2017 17:43:27 -0700
> Dmitry Torokhov wrote:
>
> > Hi Michal,
> >
> > On Tue, May 09, 2017 at 09:14:18PM +0200, Michal Suchanek wrote:
> > > There is nothing mac-specific about this driver. Non-mac hardware
> > > with subo
Le 25/05/2017 à 05:36, Balbir Singh a écrit :
Today our patching happens via direct copy and
patch_instruction. The patching code is well
contained in the sense that copying bits are limited.
While considering implementation of CONFIG_STRICT_RWX,
the first requirement is to a create another ma
On Sun, May 28, 2017 at 11:47:58AM +0200, Michal Suchanek wrote:
> On Tue, 9 May 2017 17:43:27 -0700
> Dmitry Torokhov wrote:
>
> > Hi Michal,
> >
> > On Tue, May 09, 2017 at 09:14:18PM +0200, Michal Suchanek wrote:
> > > There is nothing mac-specific about this driver. Non-mac hardware
> > > wi
Le 25/05/2017 à 05:36, Balbir Singh a écrit :
Today our patching happens via direct copy and
patch_instruction. The patching code is well
contained in the sense that copying bits are limited.
While considering implementation of CONFIG_STRICT_RWX,
the first requirement is to a create another ma
Le 25/05/2017 à 05:36, Balbir Singh a écrit :
Today our patching happens via direct copy and
patch_instruction. The patching code is well
contained in the sense that copying bits are limited.
While considering implementation of CONFIG_STRICT_RWX,
the first requirement is to a create another ma
On Tue, 9 May 2017 17:43:27 -0700
Dmitry Torokhov wrote:
> Hi Michal,
>
> On Tue, May 09, 2017 at 09:14:18PM +0200, Michal Suchanek wrote:
> > There is nothing mac-specific about this driver. Non-mac hardware
> > with suboptimal built-in pointer devices exists.
> >
> > This makes it possible to
23 matches
Mail list logo
