On Thu, 25 May 2017 13:36:42 +1000
Balbir Singh wrote:
> Enable STRICT_KERNEL_RWX for PPC64/BOOK3S
>
> These patches enable RX mappings of kernel text.
> rodata is mapped RX as well as a trade-off, there
> are more details in the patch description
>
> As a prerequisite for R/O text, patch_instr
On Thursday 25 May 2017 11:46 AM, Michael Ellerman wrote:
Michael Neuling writes:
On Wed, 2017-05-24 at 14:26 +0530, Aneesh Kumar K.V wrote:
Michael Neuling writes:
Currently if you disable CONFIG_PPC_RADIX_MMU you'll crash on boot on
a P9. This is because we still set MMU_FTR_TYPE_RADIX
Michael Bringmann writes:
> On 05/24/2017 06:19 AM, Michael Ellerman wrote:
>> Michael Bringmann writes:
>>>
>>> With or without 3af229f2071f, we would still need to add something,
>>> somewhere to add new
>>> bits to the 'node_possible_map'. That is not being done.
>>
>> You mustn't add bits
Michael Neuling writes:
> On Wed, 2017-05-24 at 14:26 +0530, Aneesh Kumar K.V wrote:
>> Michael Neuling writes:
>>
>> > Currently if you disable CONFIG_PPC_RADIX_MMU you'll crash on boot on
>> > a P9. This is because we still set MMU_FTR_TYPE_RADIX via
>> > ibm,pa-features and MMU_FTR_TYPE_RADI
Define interfaces (wrappers) to the 'copy' and 'paste' instructions
(which are new in PowerISA 3.0). These are intended to be used to
by NX driver(s) to submit Coprocessor Request Blocks (CRBs) to the
NX hardware engines.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v4]
- Export symb
Define an interface to open a VAS send window. This interface is
intended to be used the Nest Accelerator (NX) driver(s) to open
a send window and use it to submit compression/encryption requests
to a VAS receive window.
The receive window, identified by the [vasid, cop] parameters, must
already b
Define the vas_win_close() interface which should be used to close a
send or receive windows.
While the hardware configurations required to open send and receive windows
differ, the configuration to close a window is the same for both. So we use
a single interface to close the window.
Signed-off-
Define the vas_rx_win_open() interface. This interface is intended to be
used by the Nest Accelerator (NX) driver(s) to setup receive windows for
one or more NX engines (which implement compression/encryption algorithms
in the hardware).
Follow-on patches will provide an interface to close the win
Define helpers to allocate/free VAS window objects. These will
be used in follow-on patches when opening/closing windows.
Signed-off-by: Sukadev Bhattiprolu
---
arch/powerpc/platforms/powernv/vas-window.c | 61 +
1 file changed, 61 insertions(+)
diff --git a/arch/pow
Define helpers to initialize window context registers of the VAS
hardware. These will be used in follow-on patches when opening/closing
VAS windows.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v5]
- Fix: Copy the FIFO address into LFIFO_BAR register as is (don't
shift addre
Define macros for the VAS hardware registers and bit-fields as well
as couple of data structures needed by the VAS driver.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v4]
- [Michael Neuling] Move VAS code to arch/powerpc; Reorg vas.h and
vas-internal.h to kernel and uapi ve
Implement vas_init() and vas_exit() functions for a new VAS module.
This VAS module is essentially a library for other device drivers
and kernel users of the NX coprocessors like NX-842 and NX-GZIP.
In the future this will be extended to add support for user space
to access the NX coprocessors.
VA
Define some helper functions to access the MMIO regions. We use these
in a follow-on patches to read/write VAS hardware registers. These
helpers are also used to later issue 'paste' instructions to submit
requests to the NX hardware engines.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog [v5]:
Move the GET_FIELD and SET_FIELD macros to vas.h as VAS and other
users of VAS, including NX-842 can use those macros.
There is a lot of related code between the VAS/NX kernel drivers
and skiboot. For consistency switch the order of parameters in
SET_FIELD to match the order in skiboot.
Signed-of
Power9 introduces a hardware subsystem referred to as the Virtual
Accelerator Switchboard (VAS). VAS allows kernel subsystems and user
space processes to directly access the Nest Accelerator (NX) engines
which implement compression and encryption algorithms in the hardware.
NX has been in Power pr
Tyrel Datwyler [tyr...@linux.vnet.ibm.com] wrote:
> > + vinst = &vas_instances[0];
> > + for_each_node_by_name(dn, "vas") {
> > + rc = init_vas_instance(dn, vinst);
> > + if (rc) {
> > + pr_err("Error %d initializing VAS instance %ld\n", rc,
> > +
On Wed, May 24, 2017 at 11:36 PM, Paul Clarke wrote:
> On 05/23/2017 06:45 PM, Matt Brown wrote:
>> The xor_vmx.c file is used for the RAID5 xor operations. In these functions
>> altivec is enabled to run the operation and then disabled. However due to
>> compiler instruction reordering, altivec i
The check in hpte_find() should be < and not <= for PAGE_OFFSET
Signed-off-by: Balbir Singh
---
arch/powerpc/mm/dump_hashpagetable.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/dump_hashpagetable.c
b/arch/powerpc/mm/dump_hashpagetable.c
index c6b900f..b1c
We have the basic support in the form of patching R/O
text sections, linker scripts for extending alignment
of text data. We've also got mark_rodata_ro()
Signed-off-by: Balbir Singh
---
arch/powerpc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/K
With hash we update the bolted pte to mark it read-only. We rely
on the MMU_FTR_KERNEL_RO to generate the correct permissions
for read-only text. The radix implementation just prints a warning
in this implementation
Signed-off-by: Balbir Singh
---
arch/powerpc/include/asm/book3s/64/hash.h | 3
PAPR has pp0 in bit 55, currently we assumed that bit
pp0 is bit 0 (all bits in IBM order). This patch fixes
the pp0 bits for both these routines that use H_PROTECT
Signed-off-by: Balbir Singh
---
arch/powerpc/platforms/pseries/lpar.c | 13 +++--
1 file changed, 11 insertions(+), 2 delet
For CONFIG_STRICT_KERNEL_RWX align __init_begin to 16M.
We use 16M since its the larger of 2M on radix and 16M
on hash for our linear mapping. The plan is to have
.text, .rodata and everything upto __init_begin marked
as RX. Note we still have executable read only data.
We could further align read
Move from mwrite() to patch_instruction() for xmon for
breakpoint addition and removal.
Signed-off-by: Balbir Singh
---
arch/powerpc/xmon/xmon.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index f11f656..0952014 1
arch_arm/disarm_probe use direct assignment for copying
instructions, replace them with patch_instruction
Signed-off-by: Balbir Singh
---
arch/powerpc/kernel/kprobes.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kpro
Today our patching happens via direct copy and
patch_instruction. The patching code is well
contained in the sense that copying bits are limited.
While considering implementation of CONFIG_STRICT_RWX,
the first requirement is to a create another mapping
that will allow for patching. We create the
Enable STRICT_KERNEL_RWX for PPC64/BOOK3S
These patches enable RX mappings of kernel text.
rodata is mapped RX as well as a trade-off, there
are more details in the patch description
As a prerequisite for R/O text, patch_instruction
is moved over to using a separate mapping that
allows write to k
Michael Neuling writes:
> On Wed, 2017-05-24 at 14:26 +0530, Aneesh Kumar K.V wrote:
>> Michael Neuling writes:
>>
>> > Currently if you disable CONFIG_PPC_RADIX_MMU you'll crash on boot on
>> > a P9. This is because we still set MMU_FTR_TYPE_RADIX via
>> > ibm,pa-features and MMU_FTR_TYPE_RADI
On Wed, 2017-05-24 at 14:26 +0530, Aneesh Kumar K.V wrote:
> Michael Neuling writes:
>
> > Currently if you disable CONFIG_PPC_RADIX_MMU you'll crash on boot on
> > a P9. This is because we still set MMU_FTR_TYPE_RADIX via
> > ibm,pa-features and MMU_FTR_TYPE_RADIX is what's used for code patchin
Looks good to me
On 23/05/17 14:05, Oliver O'Halloran wrote:
From: Anton Blanchard
Adds support for removing bolted (i.e kernel linear mapping) mappings on
powernv. This is needed to support memory hot unplug operations which
are required for the teardown of DAX/PMEM devices.
Reviewed-by: Ra
On 05/24/2017 06:19 AM, Michael Ellerman wrote:
> Michael Bringmann writes:
>
>> On 05/23/2017 04:49 PM, Reza Arbab wrote:
>>> On Tue, May 23, 2017 at 03:05:08PM -0500, Michael Bringmann wrote:
On 05/23/2017 10:52 AM, Reza Arbab wrote:
> On Tue, May 23, 2017 at 10:15:44AM -0500, Michae
I will get a log based on the latest 4.12 kernel to show what happens
one way or the other, with this patch removed.
On 05/24/2017 09:36 AM, Reza Arbab wrote:
> On Tue, May 23, 2017 at 05:44:23PM -0500, Michael Bringmann wrote:
>> On 05/23/2017 04:49 PM, Reza Arbab wrote:
>>> On Tue, May 23, 2017
- log an error message when registration fails and no error code listed
in the switch is returned
- translate the hv error code to posix error code and return it from
fw_register
- return the posix error code from fw_register to the process writing
to sysfs
- return EEXIST on re-registration
On Tue, May 23, 2017 at 05:44:23PM -0500, Michael Bringmann wrote:
On 05/23/2017 04:49 PM, Reza Arbab wrote:
On Tue, May 23, 2017 at 03:05:08PM -0500, Michael Bringmann wrote:
On 05/23/2017 10:52 AM, Reza Arbab wrote:
On Tue, May 23, 2017 at 10:15:44AM -0500, Michael Bringmann wrote:
+static
On 05/23/2017 06:45 PM, Matt Brown wrote:
> The xor_vmx.c file is used for the RAID5 xor operations. In these functions
> altivec is enabled to run the operation and then disabled. However due to
> compiler instruction reordering, altivec instructions are being run before
> enable_altivec() and aft
Abdul Haleem writes:
> Hi Cyril,
>
> I see a similar trace, but with 'tm-signal-stack' test for mainline
> kernel 4.12.0-rc1 on PowerVM LPAR.
I can't reproduce this here.
Can you please retest on rc2.
Also please include the exact version of the test (it prints it), and
what toolchain you built
On 05/24/2017 11:29 AM, Abdul Haleem wrote:
> Hi
>
> commit cf22cd5f3a: dm crypt: add cryptographic data integrity protection
> suspected to be bad.
Isn't this false positive? That commit changes only dm-crypt and that module
seems not to be even loaded...
(Moreover config has disabled block inte
Michael Bringmann writes:
> On 05/23/2017 04:49 PM, Reza Arbab wrote:
>> On Tue, May 23, 2017 at 03:05:08PM -0500, Michael Bringmann wrote:
>>> On 05/23/2017 10:52 AM, Reza Arbab wrote:
On Tue, May 23, 2017 at 10:15:44AM -0500, Michael Bringmann wrote:
> +static void setup_nodes(void)
>>
POWER9 introduces a new mode for the decrementer register, called
large decrementer mode, in which the decrementer counter is 56 bits
wide rather than 32, and reads sign-extend rather than zero-extending.
Since KVM code reads and writes the host decrementer value in a few
places, it needs to be aw
This allows userspace (e.g. QEMU) to enable large decrementer mode
for the guest, by setting the LPCR_LD bit in the guest LPCR value.
With this, the guest exit code saves 64 bits of the guest DEC value
on exit. Other places that use the guest DEC value check the LPCR_LD
bit in the guest LPCR value
One of the new features of POWER9 is that the decrementer (the
facility that provides an interrupt after a programmable length of
time) has been increased in size from 32 bits to 56 bits, allowing
time intervals of up to about 814 days, compared to 4 seconds
previously. This patch series adds supp
Hi
commit cf22cd5f3a: dm crypt: add cryptographic data integrity protection
suspected to be bad.
Test : trinity
Machine : Power 8 (LPAR)
kernel : 4.12.0-rc2-next-20170523
Config : attached
Unable to handle kernel paging request for data at address 0x
Faulting instruction address: 0xc
Jeremy Kerr writes:
> Change ac29c64089b7 swapped _PAGE_USER for _PAGE_PRIVILEGED, and
> introduced check_pte_access() which denied kernel access to
> non-_PAGE_PRIVILEGED pages.
>
> However, it didn't add _PAGE_PRIVILEGED to the hash fault handler for
> spufs' kernel accesses, so the DMAs requir
Michael Neuling writes:
> Currently if you disable CONFIG_PPC_RADIX_MMU you'll crash on boot on
> a P9. This is because we still set MMU_FTR_TYPE_RADIX via
> ibm,pa-features and MMU_FTR_TYPE_RADIX is what's used for code patching
> in much of the asm code (ie. slb_miss_realmode)
>
> This patch fi
From: Sebastian Andrzej Siewior
set_subcores_per_core() holds get_online_cpus() while invoking stop_machine().
stop_machine() invokes get_online_cpus() as well. This is correct, but
prevents the conversion of the hotplug locking to a percpu rwsem.
Use stop_machine_cpuslocked() to avoid the nest
From: Sebastian Andrzej Siewior
kvmppc_alloc_host_rm_ops() holds get_online_cpus() while invoking
cpuhp_setup_state_nocalls().
cpuhp_setup_state_nocalls() invokes get_online_cpus() as well. This is
correct, but prevents the conversion of the hotplug locking to a percpu
rwsem.
Use cpuhp_setup_st
of_mm_gpiochip_add_data() generates an Oops for NULL pointer dereference.
of_mm_gpiochip_add_data() calls mm_gc->save_regs() before
setting the data, therefore ->save_regs() cannot use gpiochip_get_data()
Fixes: 937daafca774b ("powerpc: simple-gpio: use gpiochip data pointer")
Cc: sta...@vger.ker
Currently if you disable CONFIG_PPC_RADIX_MMU you'll crash on boot on
a P9. This is because we still set MMU_FTR_TYPE_RADIX via
ibm,pa-features and MMU_FTR_TYPE_RADIX is what's used for code patching
in much of the asm code (ie. slb_miss_realmode)
This patch fixes the problem by stopping MMU_FTR_T
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