On 2017-05-02 01:22:06 Tue, Daniel Axtens wrote:
> Michael Ellerman writes:
>
> > Daniel Axtens writes:
> >>> diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
> >>> index a1475e6..b23b323 100644
> >>> --- a/arch/powerpc/kernel/mce.c
> >>> +++ b/arch/powerpc/kernel/mce.c
> >>> @
Hi all,
The linux-next build (powerpc allyesconfig) produced these warnings
(and have for a while):
arch/powerpc/kvm/book3s_pr_papr.c: In function 'kvmppc_h_pr_enter':
arch/powerpc/kvm/book3s_pr_papr.c:53:2: warning: ignoring return value of
'copy_from_user', declared with attribute warn_unused_
On 05/02/2017 10:34 AM, Guenter Roeck wrote:
> On 05/01/2017 09:35 PM, Shilpasri G Bhat wrote:
>> Hi Guenter,
>>
>> On 04/28/2017 06:59 PM, Guenter Roeck wrote:
>>> On 04/27/2017 10:59 PM, Shilpasri G Bhat wrote:
Add support for adding min/max values for the inband sensors copied by
OCC
Add __GFP_ACCOUNT to __hugepte_alloc()
Signed-off-by: Balbir Singh
---
arch/powerpc/mm/hugetlbpage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index a4f33de..94e56b1 100644
--- a/arch/powerpc/mm/hugetlbpage.c
Add support in pte_alloc_one() and pgd_alloc() by
passing __GFP_ACCOUNT in the flags
Signed-off-by: Balbir Singh
---
arch/powerpc/include/asm/nohash/32/pgalloc.h | 3 ++-
arch/powerpc/mm/pgtable_32.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powe
Introduce a helper pgtable_gfp_flags() which
just returns the current gfp flags and adds
__GFP_ACCOUNT to account for page table allocation.
The generic helper is added to include/asm/pgalloc.h
and has two variants - WARNING ugly bits ahead
1. If the header is included from a module, no check
for
(3e79ec7 arch: x86: charge page tables to kmemcg) added support for page
table accounting). This patch is the second iteration to add
support, in the earlier iteration only book3s 64 bit was supported.
This iteration adds support for booke/3s/32 and 64 bit.
There is some ugliness in this patchset,
On 05/01/2017 09:35 PM, Shilpasri G Bhat wrote:
Hi Guenter,
On 04/28/2017 06:59 PM, Guenter Roeck wrote:
On 04/27/2017 10:59 PM, Shilpasri G Bhat wrote:
Add support for adding min/max values for the inband sensors copied by
OCC to main memory. And also add current(mA) sensors to the list.
Sig
Hi Guenter,
On 04/28/2017 06:59 PM, Guenter Roeck wrote:
> On 04/27/2017 10:59 PM, Shilpasri G Bhat wrote:
>> Add support for adding min/max values for the inband sensors copied by
>> OCC to main memory. And also add current(mA) sensors to the list.
>>
>> Signed-off-by: Shilpasri G Bhat
>> ---
>>
Thanks for upadating the patch with review comments Alastair.
Alastair D'Silva writes:
> From: Alastair D'Silva
>
> In some situations, a faulty AFU slice may create an interrupt storm of
> slice errors, rendering the machine unusable. Since these interrupts are
> informational only, present t
From: Claudiu Manoil
Unlike PPC builds, ARM builds need following headers
explicitly:
+#include for ioread32be()
+#includefor udelay()
Signed-off-by: Claudiu Manoil
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/dpaa_sys.h | 2 ++
1 file changed, 2 insertions(+)
From: Madalin Bucur
Signed-off-by: Madalin Bucur
Signed-off-by: Claudiu Manoil
[Stuart: changed to use ARCH_LAYERSCAPE]
Signed-off-by: Stuart Yoder
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/
From: Madalin Bucur
Add revision 3.2 of the QBMan block. This is the version
for LS1043A and LS1046A SoCs.
Signed-off-by: Madalin Bucur
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/qman_ccsr.c | 2 ++
drivers/soc/fsl/qbman/qman_priv.h | 1 +
2 files changed, 3 insertions(+)
diff --gi
Rework ioremap() for PPC and ARM. The PPC devices require a
non-coherent mapping while ARM will work with a non-cachable/write
combine mapping.
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/bman_portal.c | 12 +---
drivers/soc/fsl/qbman/qman_portal.c | 12 +---
2 files chan
From: Valentin Rothberg
The Kconfig symbol for 32bit ARM is 'ARM', not 'ARM32'.
Signed-off-by: Valentin Rothberg
Signed-off-by: Claudiu Manoil
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/dpaa_sys.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/qb
From: Madalin Bucur
Signed-off-by: Madalin Bucur
Signed-off-by: Claudiu Manoil
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/bman.c | 22 ++
drivers/soc/fsl/qbman/qman.c | 38 ++
2 files changed, 60 insertions(+)
diff --git a/driv
From: Madalin Bucur
Replace PPC specific set/clear_bits API with standard
bit twiddling so driver is portalable outside PPC.
Signed-off-by: Madalin Bucur
Signed-off-by: Claudiu Manoil
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/bman.c | 2 +-
drivers/soc/fsl/qbman/qman.c | 8
Updates the QMan and BMan device tree bindings for reserved memory
nodes. This makes the reserved memory allocation compatiable with
the shared-dma-pool usage.
Signed-off-by: Roy Pledge
---
Documentation/devicetree/bindings/soc/fsl/bman.txt | 12 +-
Documentation/devicetree/bindings/soc/
Use the shared-memory-pool mechanism for frame queue descriptor and
packed frame descriptor record area allocations.
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/qman_ccsr.c | 138 +-
drivers/soc/fsl/qbman/qman_priv.h | 4 +-
drivers/soc/fsl/qbman/qma
From: Claudiu Manoil
Not relevant and arch dependent. Overkill for PPC.
Signed-off-by: Claudiu Manoil
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/dpaa_sys.h | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index
This patch series enables DPAA1 QBMan devices for ARM and
ARM64 architectures. This allows the LS1043A and LS1046A to use
QBMan functionality.
Changes since v2:
Fixed some misspellings
Added 'no-map' constraint to device tree bindings
Described ordering contraint on regions in the device tree
Remo
Use the shared-memory-pool mechanism for free buffer proxy record
area allocation.
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/bman_ccsr.c | 35 ++-
drivers/soc/fsl/qbman/bman_priv.h | 3 +++
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/
On 4/23/2017 9:47 PM, Scott Wood wrote:
> On Wed, 2017-04-19 at 16:48 -0400, Roy Pledge wrote:
>> Rework ioremap() for PPC and ARM. The PPC devices require a
>> non-coherent mapping while ARM will work with a non-cachable/write
>> combine mapping.
>>
>> Signed-off-by: Roy Pledge
>> ---
>> drivers
On Mon, 2017-05-01 at 09:46 +0200, christophe leroy wrote:
>
> Le 30/04/2017 à 08:48, Scott Wood a écrit :
> > On Thu, Mar 09, 2017 at 10:42:04AM +0100, Christophe Leroy wrote:
> > >
> > > @@ -625,6 +641,14 @@ int cpm1_gpiochip_add16(struct device_node *np)
> > >
> > > spin_lock_init(&cpm1_gc-
Michael Ellerman writes:
> Daniel Axtens writes:
>>> diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
>>> index a1475e6..b23b323 100644
>>> --- a/arch/powerpc/kernel/mce.c
>>> +++ b/arch/powerpc/kernel/mce.c
>>> @@ -221,6 +221,8 @@ static void machine_check_process_queued_event
This patch updates the machine check handler of Linux kernel to
handle the e6500 architecture case. In e6500 core, L1 Data Cache Write
Shadow Mode (DCWS) register is not implemented but L1 data cache always
runs in write shadow mode. So, on L1 data cache parity errors, hardware
will automatically i
OPAL_CALL uses SRR[01] with MSR_RI=1, which gets corrupted if there
is an interleaving system reset or machine check interrupt.
Use HSRR[01] instead, which does not require MSR_RI=0.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/platforms/powernv/opal-wrappers.S | 6 +++---
1 file changed, 3
FIXUP_ENDIAN uses SRR[01] with MSR_RI=1, which gets corrupted if there
is an interleaving system reset or machine check interrupt.
Set MSR_RI=0 before setting SRRs. The rfid will restore MSR.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/boot/ppc_asm.h| 12 +++-
arch/powerpc/i
Hi,
These fixes are more minimal, and split up properly since last post.
Also accounted for Ben's comment of using HSRRs rather than disabling
RI for OPAL_CALL.
This will still increase cost of opal calls a bit due to new mtmsr in
FIXUP_ENDIAN return.
I have a few more patches that reduce overhe
t;
> url:
> https://github.com/0day-ci/linux/commits/Balbir-Singh/powerpc-mm-book-e-3s-64-Add-page-table-accounting/20170501-143900
> base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
> config: powerpc-virtex5_defconfig (attached as .config)
> compiler: powerpc-
-table-accounting/20170501-143900
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-virtex5_defconfig (attached as .config)
compiler: powerpc-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget
https://raw.githubusercontent.com/01org/lkp
-table-accounting/20170501-143900
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-virtex5_defconfig (attached as .config)
compiler: powerpc-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget
https://raw.githubusercontent.com/01org/lkp
Le 30/04/2017 à 08:48, Scott Wood a écrit :
On Thu, Mar 09, 2017 at 10:42:04AM +0100, Christophe Leroy wrote:
This patch allows the use of IRQ to notify the change of GPIO status
on MPC8xx CPM IO ports. This then allows to associate IRQs to GPIOs
in the Device Tree.
Ex:
CPM1_PIO_C: gp
This patch allows the use of IRQ to notify the change of GPIO status
on MPC8xx CPM IO ports. This then allows to associate IRQs to GPIOs
in the Device Tree.
Ex:
CPM1_PIO_C: gpio-controller@960 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-c";
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