Generic core VM already prints these information in the log
buffer, hence there is no need for a second print. This just
removes the second print from arch powerpc NUMA init path.
Before the patch:
$dmesg | grep "Initmem"
numa: Initmem setup node 0 [mem 0x-0x]
numa: Initmem setup
Le 03/04/2017 à 15:05, Frederic Barrat a écrit :
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
- Dedic
Rob Herring writes:
> On Wed, Apr 5, 2017 at 9:32 AM, Nicholas Piggin wrote:
>> On Wed, 5 Apr 2017 08:35:06 -0500
>> Rob Herring wrote:
>>
>>> On Wed, Apr 5, 2017 at 7:37 AM, Nicholas Piggin wrote:
>>> > Introduce primitives for FDT parsing. These will be used for powerpc
>>> > cpufeatures nod
Mahesh J Salgaonkar writes:
> From: Mahesh Salgaonkar
>
> It will be used in arch/powerpc/kvm/book3s_hv.c KVM module.
>
> Signed-off-by: Mahesh Salgaonkar
> ---
> arch/powerpc/kernel/mce.c |1 +
> 1 file changed, 1 insertion(+)
Thanks.
Acked-by: Michael Ellerman
cheers
Heiko Carstens writes:
> On Fri, Mar 24, 2017 at 03:19:52PM -0400, Pavel Tatashin wrote:
>> If we are using deferred struct page initialization feature, most of
>> "struct page"es are getting initialized after other CPUs are started, and
>> hence we are benefiting from doing this job in parallel.
> On 07-Apr-2017, at 2:14 AM, Tyrel Datwyler wrote:
>
> On 04/06/2017 03:27 AM, Sachin Sant wrote:
>> On a POWER8 LPAR running 4.11.0-rc5, a hot unplug operation on
>> any I/O adapter results in the following warning
>
> I remember you mentioning this when the issue was brought up for CPUs. I
>
Tyrel Datwyler writes:
> On 04/06/2017 03:27 AM, Sachin Sant wrote:
>> On a POWER8 LPAR running 4.11.0-rc5, a hot unplug operation on
>> any I/O adapter results in the following warning
>>
>> This problem has been in the code for some time now. I had first seen this in
>> -next tree.
>>
>> [ 2
This just adds user space exported ABI definitions for 2MB, 16MB, 1GB,
16GB non default huge page sizes to be used with mmap() system call.
Signed-off-by: Anshuman Khandual
---
These defined values will be used along with MAP_HUGETLB while calling
mmap() system call if the desired HugeTLB page si
On 04/07/2017 12:33 AM, LEROY Christophe wrote:
> Hi
>
> Anshuman Khandual a écrit :
>
>> This just adds user space exported ABI definitions for 2MB, 16MB, 1GB,
>> 16GB non default huge page sizes to be used with mmap() system call.
>
> Why not add all possible huge page sizes ?
> For instance
On Thu, 6 Apr 2017 12:41:52 -0700
Linus Torvalds wrote:
> On Thu, Apr 6, 2017 at 12:23 PM, Peter Zijlstra wrote:
> >
> > Something like so then. According to the SDM mwait is a no-op if we do
> > not execute monitor first. So this variant should get the first
> > iteration without expensive inst
On 06/03/17 12:54, Alexey Kardashevskiy wrote:
> On 06/03/17 10:22, Gavin Shan wrote:
>> On Fri, Mar 03, 2017 at 04:59:11PM +1100, Alexey Kardashevskiy wrote:
>>> On 03/03/17 15:47, Russell Currey wrote:
eeh_handle_special_event() is called when an EEH event is detected but
can't be narro
Show branch type in callchain entry. The branch type is printed
with other LBR information (such as cycles/abort/...).
One example:
perf report --branch-history --stdio --no-children
-23.60%--main div.c:42 (RET cycles:2)
compute_flag div.c:28 (RET cycles:2)
compute_flag div.c:27
Show the branch type statistics at the end of perf report --stdio.
For example:
perf report --stdio
JCC forward: 27.7%
JCC backward: 9.8%
JMP: 0.0%
IND_JMP: 6.5%
CALL: 26.6%
IND_CALL: 0.0%
RET: 29.3%
IRET: 0.0%
CROSS_4K: 0.0%
CROS
The option indicates the kernel to save branch type during sampling.
One example:
perf record -g --branch-filter any,save_type
Signed-off-by: Jin Yao
---
tools/perf/Documentation/perf-record.txt | 1 +
tools/perf/util/parse-branch-options.c | 1 +
2 files changed, 2 insertions(+)
diff --git
Perf already has support for disassembling the branch instruction
and using the branch type for filtering. The patch just records
the branch type in perf_branch_entry.
Before recording, the patch converts the x86 branch classification
to common branch classification and compute for checking if the
It is often useful to know the branch types while analyzing branch
data. For example, a call is very different from a conditional branch.
Currently we have to look it up in binary while the binary may later
not be available and even the binary is available but user has to take
some time. It is ver
v2:
---
1. Use 4 bits in perf_branch_entry to record branch type.
2. Pull out some common branch types from FAR_BRANCH. Now the branch
types defined in perf_event.h:
PERF_BR_NONE : unknown
PERF_BR_JCC_FWD : conditional forward jump
PERF_BR_JCC_BWD : conditional backward jump
PERF_BR_J
Hari Bathini writes:
> In case of fadump, capture (fadump) kernel boots like a normal kernel.
> While this has its advantages, the capture kernel would initialize all
> the components like normal kernel, which may not necessarily be needed
> for a typical dump capture kernel. So, fadump capture k
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/reg.h | 2 ++
arch/powerpc/kernel/traps.c| 19 ++-
2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index fc879fd6bdae..d9e52a1336a6 1006
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/traps.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index ff365f9de27a..a34d8bf3dbe4 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1440,6 +1440
No real change except add register definitions and facility
unavailable type names.
Nicholas Piggin (2):
powerpc/64s: Add msgp facility unavailable log string
powerpc/64s: Add SCV FSCR bit for ISA v3.0
arch/powerpc/include/asm/reg.h | 2 ++
arch/powerpc/kernel/traps.c| 18 ++
Hi Michael,
We'll also need a similar patch for the t10dif code that went in to
Herbert's next.
I will do a patch once I get my development environment up and going
again.
Regards,
Daniel
Michael Ellerman writes:
> In crc32c_vpmsum() we call enable_kernel_altivec() without first
> disabling p
On 04/06/2017 03:27 AM, Sachin Sant wrote:
> On a POWER8 LPAR running 4.11.0-rc5, a hot unplug operation on
> any I/O adapter results in the following warning
>
> This problem has been in the code for some time now. I had first seen this in
> -next tree.
>
> [ 269.589441] rpadlpar_io: slot PHB 7
On Thu, Apr 6, 2017 at 12:23 PM, Peter Zijlstra wrote:
>
> Something like so then. According to the SDM mwait is a no-op if we do
> not execute monitor first. So this variant should get the first
> iteration without expensive instructions.
No, the problem is that we *would* have executed a prior
On Thu, Apr 06, 2017 at 10:31:46AM -0700, Linus Torvalds wrote:
> And we'd probably want to make it even more strict, in that soem mwait
> implementations might simply not be very good for short waits.
Yeah, we need to find something that works; assuming its beneficial at
all on modern chips.
> >
Hi
Anshuman Khandual a écrit :
This just adds user space exported ABI definitions for 2MB, 16MB, 1GB,
16GB non default huge page sizes to be used with mmap() system call.
Why not add all possible huge page sizes ?
For instance the 8xx (only) supports 512k and 8M hugepages
Christophe
Sign
From: Aravinda Prasad
Enhance KVM to cause a guest exit with KVM_EXIT_NMI
exit reason upon a machine check exception (MCE) in
the guest address space if the KVM_CAP_PPC_FWNMI
capability is enabled (instead of delivering a 0x200
interrupt to guest). This enables QEMU to build error
log and deliver
From: Mahesh Salgaonkar
It will be used in arch/powerpc/kvm/book3s_hv.c KVM module.
Signed-off-by: Mahesh Salgaonkar
---
arch/powerpc/kernel/mce.c |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
index a1475e6..e567ff1 100644
--- a/ar
From: Aravinda Prasad
This patch introduces a new KVM capability to control
how KVM behaves on machine check exception (MCE).
Without this capability, KVM redirects machine check
exceptions to guest's 0x200 vector, if the address in
error belongs to the guest. With this capability KVM
causes a gu
From: Aravinda Prasad
This series of patches add FWNMI support for KVM guests
on POWER.
Memory errors such as bit flips that cannot be corrected
by hardware is passed on to the kernel for handling
by raising machine check exception (an NMI). Upon such
machine check exceptions, if the address in
On Thu, Apr 6, 2017 at 9:36 AM, Peter Zijlstra wrote:
>
> Something like the below, which is ugly (because I couldn't be bothered
> to resolve the header recursion and thus duplicates the monitor/mwait
> functions) and broken (because it hard assumes the hardware can do
> monitor/mwait).
Yeah, I
On Thu, Apr 06, 2017 at 08:16:19AM -0700, Linus Torvalds wrote:
> In theory x86 could use monitor/mwait for it too, in practice I think
> it tends to still be too high latency (because it was originally just
> designed for the idle loop). mwait got extended to actually be useful,
> but I'm not sur
On Thu, 6 Apr 2017 15:13:53 +0100
Will Deacon wrote:
> Hi Nick,
>
> On Thu, Apr 06, 2017 at 10:59:58AM +1000, Nicholas Piggin wrote:
> > On Wed, 05 Apr 2017 07:01:57 -0700 (PDT)
> > David Miller wrote:
> >
> > > From: Nicholas Piggin
> > > Date: Tue, 4 Apr 2017 13:02:33 +1000
> > >
> > >
On Thu, Apr 6, 2017 at 7:13 AM, Will Deacon wrote:
>
> We've wrapped this up in the arm64 code as __cmpwait, and we use that
> to build smp_cond_load_acquire. It would be nice to use the same machinery
> for the conditional spinning here, unless you anticipate that we're only
> going to be spinnin
Add some explaination to the layout of vmemmap virtual address
space and how physical page mapping is only used for valid PFNs
present at any point on the system.
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Anshuman Khandual
---
Previous discussions around this http://patchwork.ozlabs.org/patch
Adds some explaination on how the vmemmap based struct page layout's
physical mapping is allocated and tracked through linked list. It
also keeps note of a possible race condition.
Signed-off-by: Anshuman Khandual
---
Previous discussions on this http://patchwork.ozlabs.org/patch/584110/
Michael
The commit (16a05bff1: powerpc: start loop at section start of
start in vmemmap_populated()) reused 'start' variable to compute
the starting address of the memory section where the given address
belongs. Then the same variable is used for iterating over starting
address of all memory sections befor
Hi Nick,
On Thu, Apr 06, 2017 at 10:59:58AM +1000, Nicholas Piggin wrote:
> On Wed, 05 Apr 2017 07:01:57 -0700 (PDT)
> David Miller wrote:
>
> > From: Nicholas Piggin
> > Date: Tue, 4 Apr 2017 13:02:33 +1000
> >
> > > On Mon, 3 Apr 2017 17:43:05 -0700
> > > Linus Torvalds wrote:
> > >
> >
On Wed, Apr 5, 2017 at 7:38 PM, Nicholas Piggin wrote:
> On Thu, 06 Apr 2017 06:58:01 +1000
> Benjamin Herrenschmidt wrote:
>
>> On Wed, 2017-04-05 at 10:58 -0500, Rob Herring wrote:
>> > Well, I'd like to avoid expanding usage of flat DT parsing in the
>> > kernel. But you could just put this fu
In crc32c_vpmsum() we call enable_kernel_altivec() without first
disabling preemption, which is not allowed:
WARNING: CPU: 9 PID: 2949 at ../arch/powerpc/kernel/process.c:277
enable_kernel_altivec+0x100/0x120
Modules linked in: dm_thin_pool dm_persistent_data dm_bio_prison dm_bufio
libcrc32c
On Wed, 2017-03-29 at 17:19:42 UTC, Frederic Barrat wrote:
> Commit 4c6d9acce1f4 ("powerpc/mm: Add hooks for cxl") converted local
> TLBIs to global if the cxl driver is active. It is necessary because
> the CAPP snoops invalidations to forward them to the PSL on the cxl
> adapter.
> However one pa
On Wed, 2017-04-05 at 11:49:09 UTC, Michael Ellerman wrote:
> From: Oliver O'Halloran
>
> When the kernel is compiled to use 64bit ABIv2 the _GLOBAL() macro does
> not include a global entry point. A function's global entry point is
> used when the function is called from a different TOC context
On Tue, 2017-04-04 at 04:56:05 UTC, Paul Mackerras wrote:
> In the past, there was only one load-with-reservation instruction,
> lwarx, and if a program attempted a lwarx on a misaligned address, it
> would take an alignment interrupt and the kernel handler would emulate
> it as though it was lwzx,
On Mon, 2017-04-03 at 09:51:44 UTC, Alistair Popple wrote:
> Nvlink2 supports address translation services (ATS) allowing devices
> to request address translations from an mmu known as the nest MMU
> which is setup to walk the CPU page tables.
>
> To access this functionality certain firmware call
On Mon, 2017-04-03 at 09:51:43 UTC, Alistair Popple wrote:
> The pnv_pci_get_{gpu|npu}_dev functions are used to find associations
> between nvlink PCIe devices and standard PCIe devices. However they
> lacked basic sanity checking which results in NULL pointer
> dereferencing if they are incorrect
On Mon, 2017-04-03 at 09:51:42 UTC, Alistair Popple wrote:
> There is of_property_read_u32_index but no u64 variant. This patch
> adds one similar to the u32 version for u64.
>
> Signed-off-by: Alistair Popple
> Acked-by: Rob Herring
Applied to powerpc next, thanks.
https://git.kernel.org/powe
On Mon, 2017-04-03 at 08:09:06 UTC, Oliver O'Halloran wrote:
> The code to fix the problem it describes was removed in c40785a and it
> uses the stupid comment style. Away it goes!
>
> Signed-off-by: Oliver O'Halloran
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c
On Mon, 2017-04-03 at 06:41:02 UTC, Anton Blanchard wrote:
> From: Anton Blanchard
>
> Early on in do_page_fault() we call store_updates_sp(), regardless of
> the type of exception. For an instruction miss this doesn't make
> sense, because we only use this information to detect if a data miss
>
On Thu, 2017-03-30 at 04:03:49 UTC, Sukadev Bhattiprolu wrote:
> >From 3ae8d1ed31b01b92b172fe20e4560cfbfab135ec Mon Sep 17 00:00:00 2001
> From: root
> Date: Mon, 27 Mar 2017 19:43:14 -0400
> Subject: [PATCH] powerpc/prom: Increase RMA size to 512MB
>
> When booting very large systems with a larg
On Wed, 2017-03-29 at 23:28:01 UTC, Matt Brown wrote:
> The HDAT data area is consumed by skiboot and turned into a device-tree. In
> some cases we would like to look directly at the HDAT. This is not possible
> through /dev/mem as it is reserved memory which is stopped by the /dev/mem
> filter. Th
On Tue, 2017-03-28 at 13:45:04 UTC, Mahesh Salgaonkar wrote:
> From: Mahesh Salgaonkar
>
> For D-side errors we print data load/store address as 'Effective address'
> that caused MC. In addition to print NIP, print kernel function name as well.
>
> After this patch the MCE console log would look
On a POWER8 LPAR running 4.11.0-rc5, a hot unplug operation on
any I/O adapter results in the following warning
This problem has been in the code for some time now. I had first seen this in
-next tree.
[ 269.589441] rpadlpar_io: slot PHB 72 removed
[ 270.589997] refcount_t: underflow; use-after
Hi Stewart,
Thanks for the review.
On Thursday 06 April 2017 02:07 PM, Stewart Smith wrote:
Madhavan Srinivasan writes:
--- a/arch/powerpc/platforms/powernv/opal-imc.c
+++ b/arch/powerpc/platforms/powernv/opal-imc.c
@@ -33,6 +33,388 @@
+static void imc_pmu_setup(struct device_node *paren
From: Borislav Petkov
Move all the EDAC core functionality behind CONFIG_EDAC and get rid of
that indirection. Update defconfigs which had it.
While at it, fix dependencies such that EDAC depends on RAS for the
tracepoints.
Signed-off-by: Borislav Petkov
Cc: linux-arm-ker...@lists.infradead.or
Hi Nicholas,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.11-rc5 next-20170406]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Nicholas-Piggin/latest-cpufeatures-patch
Thanks for reviewing the patch Fred. I have sent a v4 addressing your
comments regarding cxlflash module.
@Uma,
Can you please take a look at v4 of this patch(
https://patchwork.ozlabs.org/patch/747236/) and see if this change is ok
from cxlflash module prespetive.
Thanks,
--
Vaibhav Jain
Linu
Madhavan Srinivasan writes:
> +#define IMC_MAX_CHIPS32
> +#define IMC_MAX_PMUS 32
The max chips and PMUs we'd be able to work out from the device tre
though, right? We could just allocate the correct amount of memory on
boot.
We may hot plug/unplug CPUs, b
Madhavan Srinivasan writes:
> --- a/arch/powerpc/platforms/powernv/opal-imc.c
> +++ b/arch/powerpc/platforms/powernv/opal-imc.c
> @@ -33,6 +33,388 @@
> +static void imc_pmu_setup(struct device_node *parent)
> +{
> + struct device_node *child;
> + int pmu_count = 0, rc = 0;
> + const s
Le 05/04/2017 à 13:35, Vaibhav Jain a écrit :
During an eeh event when the cxl card is fenced and card sysfs attr
perst_reloads_same_image is set following warning message is seen in the
kernel logs:
[ 60.622727] Adapter context unlocked with 0 active contexts
[ 60.622762] [
Madhavan Srinivasan writes:
> From: Hemant Kumar
>
> Create new header file "imc-pmu.h" to add the data structures
> and macros needed for IMC pmu support.
>
> Signed-off-by: Anju T Sudhakar
> Signed-off-by: Hemant Kumar
> Signed-off-by: Madhavan Srinivasan
> ---
> arch/powerpc/include/asm/i
On Tuesday 04 April 2017 10:03 AM, Daniel Axtens wrote:
Madhavan Srinivasan writes:
From: Hemant Kumar
Adds cpumask attribute to be used by each IMC pmu. Only one cpu (any
online CPU) from each chip for nest PMUs is designated to read counters.
On CPU hotplug, dying CPU is checked to see
On Thu, Mar 30, 2017 at 10:28 AM, Matt Brown
wrote:
> The HDAT data area is consumed by skiboot and turned into a device-tree. In
> some cases we would like to look directly at the HDAT. This is not possible
> through /dev/mem as it is reserved memory which is stopped by the /dev/mem
> filter. The
On 04/06/2017 10:52 AM, David Gibson wrote:
> On Thu, Apr 06, 2017 at 02:17:22AM +0530, Mahesh J Salgaonkar wrote:
>> From: Mahesh Salgaonkar
>>
>> This patch introduces a mce hook which is invoked at the time of guest
>> exit to facilitate the host-side handling of machine check exception
>> befo
Madhavan Srinivasan writes:
> From: Hemant Kumar
>
> This patch does three things :
> - Enables "opal.c" to create a platform device for the IMC interface
>according to the appropriate compatibility string.
> - Find the reserved-memory region details from the system device tree
>and get
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