On Mon, Apr 03, 2017 at 01:23:15PM +0200, Thomas Huth wrote:
> According to the PowerISA 2.07, mtspr and mfspr should not generate
> an illegal instruction exception when being used with an undefined SPR,
> but rather treat the instruction as a NOP, inject a privilege exception
> or an emulation as
On Mon, Apr 03, 2017 at 01:28:34PM +0200, Thomas Huth wrote:
> KVM should not inject a facility unavailable exception into the guest
> when it tries to execute a mtspr/mfspr instruction for an SPR that
> is unavailable, and the vCPU is *not* running in PRoblem state.
>
> It's right that we inject
This just adds user space exported ABI definitions for both 16MB and
16GB non default huge page sizes to be used with mmap() system call.
Signed-off-by: Anshuman Khandual
---
These defined values will be used along with MAP_HUGETLB while calling
mmap() system call if the desired HugeTLB page size
Horia Geantă writes:
> Add support to submit ablkcipher and authenc algorithms
> via the QI backend:
> -ablkcipher:
> cbc({aes,des,des3_ede})
> ctr(aes), rfc3686(ctr(aes))
> xts(aes)
> -authenc:
> authenc(hmac(md5),cbc({aes,des,des3_ede}))
> authenc(hmac(sha*),cbc({aes,des,des3_ede}))
>
> caam/qi
In the past, there was only one load-with-reservation instruction,
lwarx, and if a program attempted a lwarx on a misaligned address, it
would take an alignment interrupt and the kernel handler would emulate
it as though it was lwzx, which was not really correct, but benign
since it is loading the
Madhavan Srinivasan writes:
> From: Hemant Kumar
>
> Adds cpumask attribute to be used by each IMC pmu. Only one cpu (any
> online CPU) from each chip for nest PMUs is designated to read counters.
>
> On CPU hotplug, dying CPU is checked to see whether it is one of the
> designated cpus, if yes,
* Nicholas Piggin [2017-04-04 09:52:07]:
> On Tue, 4 Apr 2017 07:54:12 +1000
> Anton Blanchard wrote:
>
> > From: Anton Blanchard
> >
> > The core of snooze_loop() continually bounces between low and very
> > low thread priority. Changing thread priorities is an expensive
> > operation that
On Tue, 4 Apr 2017 13:02:33 +1000
Nicholas Piggin wrote:
> On Mon, 3 Apr 2017 17:43:05 -0700
> Linus Torvalds wrote:
>
> > But that depends on architectures having some pattern that we *can*
> > abstract. Would some "begin/in-loop/end" pattern like the above be
> > sufficient?
>
> Yes. begi
* Anton Blanchard [2017-04-04 07:54:14]:
> From: Anton Blanchard
>
> When in the snooze_loop() we want to take up the least amount of
> resources. On my version of gcc (6.3), we end up with an extra
> branch because it predicts snooze_timeout_en to be false, whereas it
> is almost always true.
* Anton Blanchard [2017-04-04 07:54:13]:
> From: Anton Blanchard
>
> The powerpc64 kernel exception handlers have preserved thread priorities
> for a long time now, so there is no need to continually set it.
>
> Just set it once on entry and once exit.
>
> Signed-off-by: Anton Blanchard
Rev
* Anton Blanchard [2017-04-04 07:54:12]:
> From: Anton Blanchard
>
> The core of snooze_loop() continually bounces between low and very
> low thread priority. Changing thread priorities is an expensive
> operation that can negatively impact other threads on a core.
>
> All CPUs that can run Po
Hi,
So a major complaint I have is that you're changing prototypes of
functions from earlier patches.
This makes my life a lot harder: I get my head around what a function is
and does and then suddenly the prototype changes, the behaviour changes,
and I have to re-evaluate everything I thought I
On Mon, 3 Apr 2017 17:43:05 -0700
Linus Torvalds wrote:
> On Mon, Apr 3, 2017 at 4:50 PM, Nicholas Piggin wrote:
> > If you have any ideas, I'd be open to them.
>
> So the idea would be that maybe we can just make those things
> explicit. IOW, instead of having that magical looping construct
Hi,
> Device tree IMC driver code parses the IMC units and their events. It
> passes the information to IMC pmu code which is placed in powerpc/perf
> as "imc-pmu.c".
>
> This patch creates only event attributes and attribute groups for the
> IMC pmus.
>
> Signed-off-by: Anju T Sudhakar
> Signed-
Hi,
> +#define IMC_MAX_CHIPS32
> +#define IMC_MAX_PMUS 32
> +#define IMC_MAX_PMU_NAME_LEN 256
I've noticed this is used as both the maximum length for event names and
event value strings. Would another name suit better?
> +
> +#define IMC_NEST_MAX_P
Hi,
> + do {
> + pages = PAGE_SIZE * i;
> + pcni->vbase[i++] = (u64)phys_to_virt(pcni->pbase +
> + pages);
> + } while (i < (pcni->size / PAGE_SIZE));
I also just noticed that
Madhavan Srinivasan writes:
> From: Hemant Kumar
>
> Parse device tree to detect IMC units. Traverse through each IMC unit
> node to find supported events and corresponding unit/scale files (if any).
>
> Here is the DTS file for reference:
>
>
> https://github.com/open-power/ima-catalog/b
Hi all,
I'm trying to get my head around these patches - at this point I'm just
doing a first pass, so I may have more substantive structural comments
later on. In the mean time - here are some minor C nits:
> + * Copyright (C) 2016 Madhavan Srinivasan, IBM Corporation.
> + * (C) 2016 H
On Mon, Apr 3, 2017 at 4:50 PM, Nicholas Piggin wrote:
>
> POWER does not have an instruction like pause. We can only set current
> thread priority, and current implementations do something like allocate
> issue cycles to threads based on relative priorities. So there should
> be at least one or t
On Mon, 2017-04-03 at 19:49 +, Roy Pledge wrote:
> On 4/3/2017 11:42 AM, Rob Herring wrote:
> >
> > On Wed, Mar 29, 2017 at 05:13:56PM -0400, Roy Pledge wrote:
> > >
> > > Updates the QMan and BMan device tree bindings for reserved memory
> > > nodes. This makes the reserved memory allocation
On Mon, 2017-04-03 at 15:52 +0100, Robin Murphy wrote:
> On 01/04/17 08:25, Scott Wood wrote:
> >
> > On Fri, 2017-03-31 at 18:55 +0100, Robin Murphy wrote:
> > >
> > > On 31/03/17 04:27, Michael Ellerman wrote:
> > > >
> > > >
> > > > Robin Murphy writes:
> > > >
> > > > >
> > > > >
> > >
On Tue, 4 Apr 2017 07:54:14 +1000
Anton Blanchard wrote:
> From: Anton Blanchard
>
> When in the snooze_loop() we want to take up the least amount of
> resources. On my version of gcc (6.3), we end up with an extra
> branch because it predicts snooze_timeout_en to be false, whereas it
> is alm
On Tue, 4 Apr 2017 07:54:12 +1000
Anton Blanchard wrote:
> From: Anton Blanchard
>
> The core of snooze_loop() continually bounces between low and very
> low thread priority. Changing thread priorities is an expensive
> operation that can negatively impact other threads on a core.
>
> All CPU
On Mon, 3 Apr 2017 08:31:30 -0700
Linus Torvalds wrote:
> On Mon, Apr 3, 2017 at 1:13 AM, Nicholas Piggin wrote:
> >
> > The loops have some restrictions on what can be used, but they are
> > intended to be small and simple so it's not generally a problem:
> > - Don't use cpu_relax.
> > - Don'
On Mon, 2017-04-03 at 23:29 +1000, Michael Ellerman wrote:
> The other option would be just to make a rule that anything EXPORT'ed
> must use _GLOBAL_TOC().
Can we enforce that somewhat at build time ?
Cheers,
Ben.
Hi Christophe,
> > - if (user_mode(regs))
> > + if (!is_exec && user_mode(regs))
>
> Shouldn't it also check 'is_write' ?
> If it is a store, is_write should be set, shouldn't it ?
Thanks, Ben had the same suggestion. I'll add that further optimisation
in a subsequent patch.
Anton
From: Anton Blanchard
When in the snooze_loop() we want to take up the least amount of
resources. On my version of gcc (6.3), we end up with an extra
branch because it predicts snooze_timeout_en to be false, whereas it
is almost always true.
Use likely() to avoid the branch and be a little nicer
From: Anton Blanchard
The powerpc64 kernel exception handlers have preserved thread priorities
for a long time now, so there is no need to continually set it.
Just set it once on entry and once exit.
Signed-off-by: Anton Blanchard
---
drivers/cpuidle/cpuidle-powernv.c | 2 +-
1 file changed,
From: Anton Blanchard
The core of snooze_loop() continually bounces between low and very
low thread priority. Changing thread priorities is an expensive
operation that can negatively impact other threads on a core.
All CPUs that can run PowerNV support very low priority, so we can
avoid the chan
> In that function, the flow is:
> pagefault_disable();
> enable_kernel_altivec();
>
> pagefault_enable();
>
> There are a few things that it would be nice (but by no means essential)
> to find out:
> - what is the difference between pagefault and prempt enable/disable
> - is it required to
On 4/3/2017 11:42 AM, Rob Herring wrote:
> On Wed, Mar 29, 2017 at 05:13:56PM -0400, Roy Pledge wrote:
>> Updates the QMan and BMan device tree bindings for reserved memory
>> nodes. This makes the reserved memory allocation compatiable with
> s/compatiable/compatible/
>
>> the shared-dma-pool usag
Anton Blanchard a écrit :
From: Anton Blanchard
Early on in do_page_fault() we call store_updates_sp(), regardless of
the type of exception. For an instruction miss this doesn't make
sense, because we only use this information to detect if a data miss
is the result of a stack expansion instru
Sorry to post in this huge email bunch.
I have most probably hit an errata in Freescale T4240 for
PPC_DISABLE_THREADS. I'm using Rev2 - T4240. Is this Errata required to be
taken care or not? Any quick help is appreciated!
My issue: I'm running line rate of Traffic to T4240 [10G of traffic on ea
On Wed, Mar 29, 2017 at 05:13:56PM -0400, Roy Pledge wrote:
> Updates the QMan and BMan device tree bindings for reserved memory
> nodes. This makes the reserved memory allocation compatiable with
s/compatiable/compatible/
> the shared-dma-pool usage.
This change is not backwards compatible. Ple
From: Anju T Sudhakar
This patch adds support for thread IMC on cpuhotplug.
When a cpu goes offline, the LDBAR for that cpu is disabled, and when it comes
back online the previous ldbar value is written back to the LDBAR for that cpu.
To register the hotplug functions for thread_imc, a new stat
From: Hemant Kumar
This patch adds the PMU functions required for event initialization,
read, update, add, del etc. for thread IMC PMU. Thread IMC PMUs are used
for per-task monitoring. These PMUs don't need any hotplugging support.
For each CPU, a page of memory is allocated and is kept static
From: Hemant Kumar
Patch adds support for detection of thread IMC events. It adds a new
domain IMC_DOMAIN_THREAD and it is determined with the help of the
compatibility string "ibm,imc-counters-thread" based on the IMC device
tree.
Signed-off-by: Anju T Sudhakar
Signed-off-by: Hemant Kumar
Sig
From: Hemant Kumar
This patch adds support for detection of core IMC events along with the
Nest IMC events. It adds a new domain IMC_DOMAIN_CORE and its determined
with the help of the compatibility string "ibm,imc-counters-core" based
on the IMC device tree.
Signed-off-by: Anju T Sudhakar
Sign
From: Hemant Kumar
Adds cpumask attribute to be used by each IMC pmu. Only one cpu (any
online CPU) from each chip for nest PMUs is designated to read counters.
On CPU hotplug, dying CPU is checked to see whether it is one of the
designated cpus, if yes, next online cpu from the same chip (for n
From: Hemant Kumar
This patch adds the PMU function to initialize a core IMC event. It also
adds cpumask initialization function for core IMC PMU. For
initialization, a 8KB of memory is allocated per core where the data
for core IMC counters will be accumulated. The base address for this
page is
From: Hemant Kumar
Since, the IMC counters' data are periodically fed to a memory location,
the functions to read/update, start/stop, add/del can be generic and can
be used by all IMC PMU units.
This patch adds a set of generic imc pmu related event functions to be
used by each imc pmu unit. Ad
From: Hemant Kumar
Device tree IMC driver code parses the IMC units and their events. It
passes the information to IMC pmu code which is placed in powerpc/perf
as "imc-pmu.c".
This patch creates only event attributes and attribute groups for the
IMC pmus.
Signed-off-by: Anju T Sudhakar
Signed-
From: Hemant Kumar
Parse device tree to detect IMC units. Traverse through each IMC unit
node to find supported events and corresponding unit/scale files (if any).
Here is the DTS file for reference:
https://github.com/open-power/ima-catalog/blob/master/81E00612.4E0100.dts
The device
From: Hemant Kumar
This patch does three things :
- Enables "opal.c" to create a platform device for the IMC interface
according to the appropriate compatibility string.
- Find the reserved-memory region details from the system device tree
and get the base address of HOMER (Reserved memor
From: Hemant Kumar
Create new header file "imc-pmu.h" to add the data structures
and macros needed for IMC pmu support.
Signed-off-by: Anju T Sudhakar
Signed-off-by: Hemant Kumar
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/imc-pmu.h | 68 ++
Power9 has In-Memory-Collection (IMC) infrastructure which contains
various Performance Monitoring Units (PMUs) at Nest level (these are
on-chip but off-core), Core level and Thread level.
The Nest PMU counters are handled by a Nest IMC microcode which runs
in the OCC (On-Chip Controller) complex.
On 01/04/17 08:25, Scott Wood wrote:
> On Fri, 2017-03-31 at 18:55 +0100, Robin Murphy wrote:
>> On 31/03/17 04:27, Michael Ellerman wrote:
>>>
>>> Robin Murphy writes:
>>>
Hi Roy,
On 29/03/17 22:13, Roy Pledge wrote:
>
> Use the shared-memory-pool mechanism for frame q
Oliver O'Halloran writes:
> When the kernel is compiled to use 64bit ABIv2 the _GLOBAL() macro does not
> include a global entry point. A function's global entry point is used when the
> function is called from a different TOC context and in the kernel this
> typically means a call from a module
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
- Dedicated-Shared Process Programming Model
- Translatio
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
Point out the specific Coherent Accelerator Interface Architecture,
level 1, registers.
Code and functions specific to PSL8 (CAIA1) must be framed.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/context.c | 28 +++-
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementation for the psl9 in
a later patch.
Signed-off-by: Christophe Lombard
--
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The service layer API (in cxl.h) lists some low-level functions whose
implementation is different on PSL8, PSL9 and XSL:
- Init implementation for the adapter and the afu.
- Invalidate TLB/SLB.
- Attach process for dedicated/directed models.
-
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The mm_struct corresponding to the current task is acquired each time
an interrupt is raised. So to simplify the code, we only get the
mm_struct when attaching an AFU context to the process.
The mm_count reference is increased to ensure that t
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment. These two fields
are renamed to 'reserved' to avoid undef
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
This bit is used to cause a flash image load for programmable
CAIA-compliant implementation. If this bit is set to ‘0’, a power
cycle of the adapter is required to load a programmable CAIA-com-
pliant implementation from flash.
This field will
Hi Matt,
> The raid6 Q syndrome check has been optimised using the vpermxor
> instruction. This instruction was made available with POWER8, ISA version
> 2.07. It allows for both vperm and vxor instructions to be done in a single
> instruction. This has been tested for correctness on a ppc64le vm
KVM should not inject a facility unavailable exception into the guest
when it tries to execute a mtspr/mfspr instruction for an SPR that
is unavailable, and the vCPU is *not* running in PRoblem state.
It's right that we inject an exception when the vCPU is in PR mode, since
chapter "6.2.10 Facilit
According to the PowerISA 2.07, mtspr and mfspr should not generate
an illegal instruction exception when being used with an undefined SPR,
but rather treat the instruction as a NOP, inject a privilege exception
or an emulation assistance exception - depending on the SPR number.
Also turn the print
On Thu, 2017-03-30 at 12:03:49 UTC, Michael Ellerman wrote:
> From: "Aneesh Kumar K.V"
>
> In followup patch we want to increase the va range which will result
> in us requiring high_slices to have more than 64 bits. To enable this
> convert high_slices to bitmap. We keep the number bits same in
On Tue, 2017-03-21 at 17:29:51 UTC, "Aneesh Kumar K.V" wrote:
> BOOKE code is dead code as per the Kconfig details. So make it simpler
> by enabling MM_SLICE only for book3s_64. The changes w.r.t nohash is just
> removing deadcode. W.r.t ppc64, 4k without hugetlb will now enable MM_SLICE.
> But tha
On Thu, 2017-03-16 at 21:05:26 UTC, Hari Bathini wrote:
> Currently, the area to preserve boot memory is reserved at the top of
> RAM. This leaves fadump vulnerable to memory hot-remove operations. As
> memory for fadump has to be reserved early in the boot process, fadump
> can't be registered aft
On Tue, 2016-04-26 at 16:49:38 UTC, yshi wrote:
> sam440ep_setup_rtc is just called by machine_device_initcall, and it calls
> i2c_register_board_info which is init too, so the lack of __init may cause
> mismatch warning when linking kernel.
>
> Signed-off-by: Yang Shi
Applied to powerpc next, t
Nvlink2 supports address translation services (ATS) allowing devices
to request address translations from an mmu known as the nest MMU
which is setup to walk the CPU page tables.
To access this functionality certain firmware calls are required to
setup and manage hardware context tables in the nvl
The pnv_pci_get_{gpu|npu}_dev functions are used to find associations
between nvlink PCIe devices and standard PCIe devices. However they
lacked basic sanity checking which results in NULL pointer
dereferencing if they are incorrect called can be harder to spot than
an explicit WARN_ON.
Signed-off
There is of_property_read_u32_index but no u64 variant. This patch
adds one similar to the u32 version for u64.
Signed-off-by: Alistair Popple
Acked-by: Rob Herring
---
drivers/of/base.c | 31 +++
include/linux/of.h | 3 +++
2 files changed, 34 insertions(+)
diff
On Mon, 2017-04-03 at 14:28 +0530, Abdul Haleem wrote:
> On Tue, 2017-03-28 at 21:00 +1100, Michael Ellerman wrote:
> > Abdul Haleem writes:
> >
> > > Hi,
> > >
> > > While running kernel self tests on ppc64, tm/tm-signal-context-chk-vsx
> > > tests fails with Oops message.
> > >
> > > I was abl
On Tue, 2017-03-28 at 21:00 +1100, Michael Ellerman wrote:
> Abdul Haleem writes:
>
> > Hi,
> >
> > While running kernel self tests on ppc64, tm/tm-signal-context-chk-vsx
> > tests fails with Oops message.
> >
> > I was able to reproduce only twice out of 20 runs on next-20170324 only.
> > so it
The code to fix the problem it describes was removed in c40785a and it
uses the stupid comment style. Away it goes!
Signed-off-by: Oliver O'Halloran
---
arch/powerpc/mm/hash_utils_64.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powe
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