[PATCH v7 7/7] powerpc/mm: Batch tlb flush when invalidating pte entries

2016-11-27 Thread Aneesh Kumar K.V
This will improve the task exit case, by batching tlb invalidates. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/radix.h | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/book3s/64/radix.h b/arch/powerpc/include/

[PATCH v7 6/7] powerpc/mm: update radix__pte_update to not do full mm tlb flush

2016-11-27 Thread Aneesh Kumar K.V
When we are updating a pte, we just need to flush the tlb mapping that pte. Right now we do a full mm flush because we don't track page size. Now that we have page size details in pte use that to do the optimized flush Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/radix.

[PATCH v7 5/7] powerpc/mm: update radix__ptep_set_access_flag to not do full mm tlb flush

2016-11-27 Thread Aneesh Kumar K.V
When we are updating a pte, we just need to flush the tlb mapping that pte. Right now we do a full mm flush because we don't track the page size. Now that we have page size details in pte use that to do the optimized flush Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/32/pg

[PATCH v7 4/7] powerpc/mm: Add radix__tlb_flush_pte

2016-11-27 Thread Aneesh Kumar K.V
Now that we have page size details encoded in pte using software pte bits, use that to find the page size needed for tlb flush. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/tlbflush-radix.h | 2 ++ arch/powerpc/mm/tlb-radix.c | 18 ++

[PATCH v7 3/7] powerpc/mm: Introduce _PAGE_LARGE software pte bits

2016-11-27 Thread Aneesh Kumar K.V
This patch adds a new software defined pte bit. We use the reserved fields of ISA 3.0 pte definition since we will only be using this on DD1 code paths. We can possibly look at removing this code later. The software bit will be used to differentiate between 64K/4K and 2M ptes. This helps in findin

[PATCH v7 2/7] powerpc/mm/hugetlb: Handle hugepage size supported by hash config

2016-11-27 Thread Aneesh Kumar K.V
W.r.t hash page table config, we support 16MB and 16GB as the hugepage size. Update the hstate_get_psize to handle 16M and 16G. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hugetlb.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/include/asm/book3s

[PATCH v7 1/7] powerpc/mm: Rename hugetlb-radix.h to hugetlb.h

2016-11-27 Thread Aneesh Kumar K.V
We will start moving some book3s specific hugetlb functions there. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/{hugetlb-radix.h => hugetlb.h} | 4 ++-- arch/powerpc/include/asm/hugetlb.h| 2 +- 2 files changed, 3 insertions(+), 3 deletio

[PATCH v7 0/7] Radix pte update tlbflush optimizations.

2016-11-27 Thread Aneesh Kumar K.V
Changes from v6: * restrict the new pte bit to radix and DD1 config Changes from V5: Switch to use pte bits to track page size. Aneesh Kumar K.V (7): powerpc/mm: Rename hugetlb-radix.h to hugetlb.h powerpc/mm/hugetlb: Handle hugepage size supported by hash config powerpc/mm: Introduce _PAG

[PATCH v3] powerpc/64be: option to use ELFv2 ABI for big endian kernels

2016-11-27 Thread Nicholas Piggin
Provide an option to use ELFv2 ABI for big endian builds. The toolchain check can't be done at configure-time, so the way this option is provided can result in unbuildable kernel on older toolchains. Being experimental expert option there isn't a need to add a lot of fallback logic to make this bui

Re: [PATCH] powerpc/boot: request no dynamic linker for boot wrapper

2016-11-27 Thread Alan Modra
On Mon, Nov 28, 2016 at 12:42:26PM +1100, Nicholas Piggin wrote: > The boot wrapper performs its own relocations and does not require > PT_INTERP segment. OK, so the kernel change is quite reasonable in isolation, but see below. > Without this option, binutils 2.28 and newer tries to create a pro

[PATCH] powerpc/boot: request no dynamic linker for boot wrapper

2016-11-27 Thread Nicholas Piggin
The boot wrapper performs its own relocations and does not require PT_INTERP segment. Without this option, binutils 2.28 and newer tries to create a program header segment due to PT_INTERP, and the link fails because there is no space for it. A recent binutils commit: https://sourceware.or

Re: [PATCH v3 11/11] powerpc: rewrite local_t using soft_irq

2016-11-27 Thread Madhavan Srinivasan
On Tuesday 15 November 2016 01:36 PM, Gabriel Paubert wrote: Hi, On Mon, Nov 14, 2016 at 11:34:52PM +0530, Madhavan Srinivasan wrote: Local atomic operations are fast and highly reentrant per CPU counters. Used for percpu variable updates. Local atomic operations only guarantee vari

[PATCH v3 4/4] powerpc/perf: macros for PowerISA v3.0 format encoding

2016-11-27 Thread Madhavan Srinivasan
Patch to add macros and contants to support the PowerISA v3.0 raw event encoding format. Couple of functions added since some of the bits fields like PMCxCOMB and THRESH_CMP has different width and location within MMCR* in PowerISA v3.0. Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/i

[PATCH v3 3/4] powerpc/perf: PowerISA v3.0 raw event format encoding

2016-11-27 Thread Madhavan Srinivasan
Patch to update the PowerISA v3.0 raw event encoding format information and add support for the same in Power9-pmu.c. Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/power9-pmu.c | 134 + 1 file changed, 134 insertions(+) diff --git a/arch/powerp

[PATCH v3 2/4] powerpc/perf: update attribute_group data structure

2016-11-27 Thread Madhavan Srinivasan
Rename the power_pmu and attribute_group variables that support PowerISA v2.07. Add a cpu feature flag check to pick the PowerISA v2.07 format structures to support. Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/power9-pmu.c | 13 - 1 file changed, 8 insertions(+), 5 delet

[PATCH v3 1/4] powerpc/perf: factor out the event format field

2016-11-27 Thread Madhavan Srinivasan
Factor out the format field structure for PowerISA v2.07. Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/isa207-common.c | 34 ++ arch/powerpc/perf/power8-pmu.c| 39 --- arch/powerpc/perf/power9-pmu.c| 39 -

[PATCH v3 0/4] Support PowerISA v3.0 PMU Raw event format

2016-11-27 Thread Madhavan Srinivasan
Patchset to factor out the PowerISA v2.07 PMU raw event format encoding and add support to the PowerISA v3.0 PMU raw event format encoding. Changelog v2: 1)Initialized return variable to avoid compile errors in pasemi_defconfig Changelog v1: 1) Initialized "mmcra" variable to avoid compile time e

Re: Kernel build issues with upstream binutils

2016-11-27 Thread Nicholas Piggin
On Sun, 27 Nov 2016 09:04:30 +1100 Anton Blanchard wrote: > Hi, > > A recent binutils commit: > > https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=1a9ccd70f9a75dc6b48d340059f28ef3550c107b > > has broken kernel builds: > > /home/anton/gcc.install/bin/ld: arch/powerpc/boot/zImage.p