Thiago Jung Bauermann writes:
> Hello Eric,
>
> Am Freitag, 16 September 2016, 14:47:13 schrieb Eric W. Biederman:
>> Mimi Zohar writes:
>> > Hi Andrew,
>> >
>> > On Wed, 2016-08-31 at 18:38 -0400, Mimi Zohar wrote:
>> >> On Wed, 2016-08-31 at 13:50 -0700, Andrew Morton wrote:
>> >> > On Tue, 3
Hello Eric,
Am Freitag, 16 September 2016, 14:47:13 schrieb Eric W. Biederman:
> Mimi Zohar writes:
> > Hi Andrew,
> >
> > On Wed, 2016-08-31 at 18:38 -0400, Mimi Zohar wrote:
> >> On Wed, 2016-08-31 at 13:50 -0700, Andrew Morton wrote:
> >> > On Tue, 30 Aug 2016 18:40:02 -0400 Mimi Zohar
wrot
Hello,
This patch causes a warning in GCC 4.6.3:
arch/powerpc/kernel/kexec_elf_64.c:211:6: error: 'initrd_load_addr' may be used
uninitialized in this function [-Werror=uninitialized]
cc1: all warnings being treated as errors
make[2]: *** [arch/powerpc/kernel/kexec_elf_64.o] Error 1
make[1]: ***
ebied...@xmission.com (Eric W. Biederman) writes:
> Mimi Zohar writes:
>
>> Hi Andrew,
>>
>> On Wed, 2016-08-31 at 18:38 -0400, Mimi Zohar wrote:
>>> On Wed, 2016-08-31 at 13:50 -0700, Andrew Morton wrote:
>>> > On Tue, 30 Aug 2016 18:40:02 -0400 Mimi Zohar
>>> > wrote:
>>> >
>>> > > The TPM P
On 09/15/2016 03:03 AM, Andy Fleming wrote:
> I agree that halt and power off mean and have always meant different
> things to the kernel. The problem is that most desktop systems,
> having halted, pass control to the BIOS which--usually--shuts off the
> power. Am I wrong about this? I've been usin
For device resource PREF bit setting under bridge 64-bit pref resource,
we need to make sure only set PREF for 64bit resource.
This patch set IORESOUCE_MEM_64 for 64bit resource during OF device
resource flags parsing.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=96261
Link: https://bugzilla
Original pci_mmap_page_range() is taking PCI BAR value aka usr_address.
Bjorn found out that it would be much simple to pass resource address
directly and avoid extra those __pci_mmap_make_offset.
In this patch:
1. in proc path: proc_bus_pci_mmap, try convert back to resource
before calling pc
Same as sparc version.
Make resource with consistent sequence
like other arch or directly from pci_read_bridge_bases(),
even when non-pref mmio is missing, or out of ordering in firmware reporting.
Just hold i = 1 for non pref mmio, and i = 2 for pref mmio.
Signed-off-by: Yinghai Lu
Cc: linuxpp
After
PCI: Let pci_mmap_page_range() take resource address
No user for __pci_mmap_make_offset in those arch.
Remove them.
Signed-off-by: Yinghai Lu
Cc: linuxppc-dev@lists.ozlabs.org
Cc: sparcli...@vger.kernel.org
Cc: linux-xte...@linux-xtensa.org
---
arch/microblaze/pci/pci-common.c | 63 ---
Mimi Zohar writes:
> Hi Andrew,
>
> On Wed, 2016-08-31 at 18:38 -0400, Mimi Zohar wrote:
>> On Wed, 2016-08-31 at 13:50 -0700, Andrew Morton wrote:
>> > On Tue, 30 Aug 2016 18:40:02 -0400 Mimi Zohar
>> > wrote:
>> >
>> > > The TPM PCRs are only reset on a hard reboot. In order to validate a
>
Hi Claudiu,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.8-rc6 next-20160916]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
[Suggest to use git(>=2.9.0) format-patch --base= (or --base=auto for
convenience) to rec
Balbir Singh writes:
> On 14/09/16 20:40, santhosh wrote:
>>
>>> Michael Ellerman writes:
>>>
On Fri, 2016-19-02 at 05:38:47 UTC, Rashmica Gupta wrote:
> Currently on PPC64 changing kernel pagesize from 4K to 64K leaves
> FORCE_MAX_ZONEORDER set to 13 - which produces a compile err
From: Nicholas Piggin
> Sent: 16 September 2016 12:59
> On Fri, 16 Sep 2016 11:43:13 +
> David Laight wrote:
>
> > From: Nicholas Piggin
> > > Sent: 16 September 2016 10:53
> > > On Thu, 15 Sep 2016 18:31:54 +0530
> > > Madhavan Srinivasan wrote:
> > >
> > > > Force use of soft_enabled_set()
Enable the drivers on the powerpc arch.
Signed-off-by: Roy Pledge
Signed-off-by: Claudiu Manoil
---
arch/powerpc/Makefile| 4 ++--
arch/powerpc/configs/dpaa.config | 1 +
drivers/soc/Kconfig | 1 +
drivers/soc/fsl/Makefile | 1 +
4 files changed, 5 insertions(+)
Add self tests for the DPAA 1.x Queue Manager driver. The tests
ensure that the driver can properly enqueue and dequeue to/from
frame queues using the QMan portal infrastructure.
Signed-off-by: Roy Pledge
Signed-off-by: Claudiu Manoil
---
drivers/soc/fsl/qbman/Kconfig | 23 ++
driver
Add a self test for the DPAA 1.x Buffer Manager driver. This
test ensures that the driver can properly acquire and release
buffers using the BMan portal infrastructure.
Signed-off-by: Roy Pledge
Signed-off-by: Claudiu Manoil
---
drivers/soc/fsl/qbman/Kconfig | 16
drivers/soc/fsl/
This driver enables the Freescale DPAA 1.x Buffer Manager block.
BMan is a hardware accelerator that manages buffer pools. It allows
CPUs and other accelerators connected to the SoC datapath to acquire
and release buffers during data processing.
Signed-off-by: Roy Pledge
Signed-off-by: Claudiu M
Add basic support for the Data Path Acceleration Architecture v1.x
(DPAA 1.x) hardware infrastructure and accelerators found on multicore
Freescale SoCs, commonly known as the QorIQ series.
CC: Roy Pledge
Claudiu Manoil (5):
soc/fsl: Introduce DPAA 1.x BMan device driver
soc/fsl: Introduce D
On Fri, 16 Sep 2016 22:06:35 +1000
Nicholas Piggin wrote:
> On Fri, 16 Sep 2016 11:57:37 +
> David Laight wrote:
>
> > From: Nicholas Piggin
> > > Sent: 16 September 2016 12:52
> > > On Fri, 16 Sep 2016 11:30:58 +
> > > David Laight wrote:
> > >
> > > > From: Nicholas Piggin
On Fri, 16 Sep 2016 11:57:37 +
David Laight wrote:
> From: Nicholas Piggin
> > Sent: 16 September 2016 12:52
> > On Fri, 16 Sep 2016 11:30:58 +
> > David Laight wrote:
> >
> > > From: Nicholas Piggin
> > > > Sent: 16 September 2016 09:58
> > > > Implementing busy wait loops with cpu
From: Nicholas Piggin
> Sent: 16 September 2016 10:53
> On Thu, 15 Sep 2016 18:31:54 +0530
> Madhavan Srinivasan wrote:
>
> > Force use of soft_enabled_set() wrapper to update paca-soft_enabled
> > wherever possisble. Also add a new wrapper function,
> > soft_enabled_set_return(),
> > added to f
From: Nicholas Piggin
> Sent: 16 September 2016 12:52
> On Fri, 16 Sep 2016 11:30:58 +
> David Laight wrote:
>
> > From: Nicholas Piggin
> > > Sent: 16 September 2016 09:58
> > > Implementing busy wait loops with cpu_relax() in callers poses
> > > some difficulties for powerpc.
> > >
> > > Fi
On Fri, 16 Sep 2016 11:43:13 +
David Laight wrote:
> From: Nicholas Piggin
> > Sent: 16 September 2016 10:53
> > On Thu, 15 Sep 2016 18:31:54 +0530
> > Madhavan Srinivasan wrote:
> >
> > > Force use of soft_enabled_set() wrapper to update paca-soft_enabled
> > > wherever possisble. Also a
On Fri, 16 Sep 2016 11:30:58 +
David Laight wrote:
> From: Nicholas Piggin
> > Sent: 16 September 2016 09:58
> > Implementing busy wait loops with cpu_relax() in callers poses
> > some difficulties for powerpc.
> >
> > First, we want to put our SMT thread into a low priority mode for the
> >
From: Nicholas Piggin
> Sent: 16 September 2016 09:58
> Implementing busy wait loops with cpu_relax() in callers poses
> some difficulties for powerpc.
>
> First, we want to put our SMT thread into a low priority mode for the
> duration of the loop, but then return to normal priority after exiting
On Thu, 15 Sep 2016 18:31:50 +0530
Madhavan Srinivasan wrote:
> Local atomic operations are fast and highly reentrant per CPU counters.
> Used for percpu variable updates. Local atomic operations only guarantee
> variable modification atomicity wrt the CPU which owns the data and
> these needs to
On Thu, 15 Sep 2016 18:32:00 +0530
Madhavan Srinivasan wrote:
> Make it explicit the interrupt masking supported
> by a gievn interrupt handler. Patch correspondingly
> extends the MASKABLE_* macros with an addition's parameter.
> "bitmask" parameter is passed to SOFTEN_TEST macro to decide
> on
On Thu, 15 Sep 2016 18:32:03 +0530
Madhavan Srinivasan wrote:
> Local atomic operations are fast and highly reentrant per CPU counters.
> Used for percpu variable updates. Local atomic operations only guarantee
> variable modification atomicity wrt the CPU which owns the data and
> these needs to
On Thu, 15 Sep 2016 18:32:02 +0530
Madhavan Srinivasan wrote:
> diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
> index 9e5e9a6d4147..ae31b1e85fdb 100644
> --- a/arch/powerpc/kernel/irq.c
> +++ b/arch/powerpc/kernel/irq.c
> @@ -209,6 +209,10 @@ notrace void arch_local_irq_rest
On Thu, 15 Sep 2016 18:32:01 +0530
Madhavan Srinivasan wrote:
> To support masking of the PMI interrupts, couple of new interrupt handler
> macros are added MASKABLE_EXCEPTION_PSERIES_OOL and
> MASKABLE_RELON_EXCEPTION_PSERIES_OOL.
>
> Couple of new irq #defs "PACA_IRQ_PMI" and "SOFTEN_VALUE_0xf
If we kexec into a new kernel on a machine where a PHB has been switched
into CAPI mode, we need to disable CAPI mode in the new kernel before
traffic begins to flow on the PHB and causes a machine checkstop.
During PHB initialisation, ask OPAL whether each PHB is in CAPI mode, and
if so, do a com
opal_pci_get_phb_capi_mode() returns OPAL_PHB_CAPI_MODE_CAPI if the PHB is
in CAPI mode, and OPAL_PHB_CAPI_MODE_PCIE if it isn't.
We're going to use this call to determine if a PHB requires a complete
reset during initialisation in order to disable CAPI mode (on sufficiently
new skiboots that supp
Signed-off-by: Andrew Donnellan
---
arch/powerpc/platforms/powernv/pci-ioda.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index c16d790..ca5e9b5 100644
--- a/arch/powerpc/platforms/
Currently, if you attempt to kexec into a new kernel from a machine with a
CAPI card and the cxl driver loaded, you are going to have an exceedingly
bad time. It turns out that the hardware doesn't really cope very well with
going through the standard Linux PCI initialisation process while a PHB is
On Thu, 15 Sep 2016 18:32:02 +0530
Madhavan Srinivasan wrote:
> New Kconfig is added "CONFIG_IRQ_DEBUG_SUPPORT" to add warn_on
> to alert the invalid transitions. Have also moved the code under
> the CONFIG_TRACE_IRQFLAGS in arch_local_irq_restore() to new Kconfig
> as suggested.
I can't tempt y
On Thu, 15 Sep 2016 18:31:59 +0530
Madhavan Srinivasan wrote:
> Currently soft_enabled is used as the flag to determine
> the interrupt state. Patch extends the soft_enabled
> to be used as a mask instead of a flag.
This should be the title of the patch, IMO. Introducing the new
mask bit is inci
On Thu, 15 Sep 2016 18:31:58 +0530
Madhavan Srinivasan wrote:
> To support addition of "bitmask" to MASKABLE_* macros,
> factor out the EXCPETION_PROLOG_1 macro.
>
> Signed-off-by: Madhavan Srinivasan
Really minor nit, but as a matter of readability of the series,
would you consider moving thi
On Thu, 15 Sep 2016 18:31:57 +0530
Madhavan Srinivasan wrote:
> Currently we use both EXCEPTION_PROLOG_1 and __EXCEPTION_PROLOG_1
> in the MASKABLE_* macros. As a cleanup, this patch makes MASKABLE_*
> to use only __EXCEPTION_PROLOG_1. There is not logic change.
>
> Signed-off-by: Madhavan Srini
On Thu, 15 Sep 2016 18:31:56 +0530
Madhavan Srinivasan wrote:
> "paca->soft_enabled" is used as a flag to mask some of interrupts.
> Currently supported flags values and their details:
>
> soft_enabledMSR[EE]
>
> 0 0 Disabled (PMI and HMI not masked)
> 1 1
Le 13/05/2016 à 08:53, Christophe Leroy a écrit :
Le 13/05/2016 à 08:16, Michael Ellerman a écrit :
On Thu, 2016-12-05 at 15:32:22 UTC, Christophe Leroy wrote:
With the ffs() function as defined in arch/powerpc/include/asm/bitops.h
GCC will not optimise the code in case of constant paramete
On Thu, 15 Sep 2016 18:31:55 +0530
Madhavan Srinivasan wrote:
> Add new soft_enabled_* manipulation function and implement
> arch_local_* using the soft_enabled_* wrappers.
>
> Signed-off-by: Madhavan Srinivasan
> ---
> arch/powerpc/include/asm/hw_irq.h | 32 ++--
>
On Thu, 15 Sep 2016 18:31:54 +0530
Madhavan Srinivasan wrote:
> Force use of soft_enabled_set() wrapper to update paca-soft_enabled
> wherever possisble. Also add a new wrapper function,
> soft_enabled_set_return(),
> added to force the paca->soft_enabled updates.
>
> Signed-off-by: Madhavan Sr
On Thu, 15 Sep 2016 18:31:53 +0530
Madhavan Srinivasan wrote:
> Move set_soft_enabled() from powerpc/kernel/irq.c to
> asm/hw_irq.c. and rename it soft_enabled_set().
> THis way paca->soft_enabled updates can be forced.
Could you just tidy up the changelog a little?
You are renaming it I assume
From: "Gautham R. Shenoy"
This patch adds a function named power_enter_stop_lite() that can
execute a stop instruction when ESL and EC bits are set to zero in the
PSSCR. The function handles the wake-up from idle at the instruction
immediately after the stop instruction.
If the flag OPAL_PM_WAK
From: "Gautham R. Shenoy"
Currently all the low-power idle states are expected to wake up
at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ
that puts the CPU to an idle state and never returns.
On ISA_300, when the ESL and EC bits in the PSSCR are zero, the
CPU is expected to wa
From: "Gautham R. Shenoy"
Hi,
The Power ISA v3.0 allows us to execute the "stop" instruction with
ESL and EC of the PSSCR set to 0. This will ensure no loss of state,
and the wakeup from the stop will happen at an instruction following
the executed stop instruction.
This patchset adds support t
On Thu, 15 Sep 2016 18:31:52 +0530
Madhavan Srinivasan wrote:
> Replace the hardcoded values used when updating
> paca->soft_enabled with IRQ_DISABLE_MASK_* #def.
> No logic change.
This could be folded with patch 1.
Reviewed-by: Nicholas Piggin
Implementing busy wait loops with cpu_relax() in callers poses
some difficulties for powerpc.
First, we want to put our SMT thread into a low priority mode for the
duration of the loop, but then return to normal priority after exiting
the loop. Dependong on the CPU design, 'HMT_low() ; HMT_medium
Hi there,
Would anyone know why I am getting the following error message in
`dmesg` on my PowerMac/Mac Mini G4:
[...]
[2.090226] PowerMac i2c bus pmu 2 registered
[2.095691] PowerMac i2c bus pmu 1 registered
[2.101016] PowerMac i2c bus mac-io 0 registered
[2.106135] PowerMac i2c b
During a machine check, the 8xx provides indication of
whether the check is due to data or instruction access, so
let's display it.
Lets also move 8xx specific handling into the new handler.
Signed-off-by: Christophe Leroy
---
v2: moved into the new handler the part conditionned by CONFIG_8xx
8xx uses a two level page table with two different linux page size
support (4k and 16k). 8xx also support two different hugepage sizes
512k and 8M. In order to support them on linux we define two different
page table layout.
The size of pages is in the PGD entry, using PS field (bits 28-29):
00 :
Today there are two implementations of hugetlbpages which are managed
by exclusive #ifdefs:
* FSL_BOOKE: several directory entries points to the same single hugepage
* BOOK3S: one upper level directory entry points to a table of hugepages
In preparation of implementation of hugepage support on the
Today powerpc64 uses a set of pgtable_caches while powerpc32 uses
standard pages when using 4k pages and a single pgtable_cache
if using other size pages.
In preparation of implementing huge pages on the 8xx, this patch
replaces the specific powerpc32 handling by the 64 bits approach.
This is don
This is v2 of patch serie is the implementation of support of
hugepages for the 8xx.
v1 of the serie was including some other fixes and
optimisations/reorganisations for the 8xx. Now the patch has been
split and this part only focuses on the implementation of
hugepages.
Compared the v1, the last p
Remove duplicate setting of the the "B" field when doing a tlbie(l).
In compute_tlbie_rb(), the "B" field is set again just before
returning the rb value to be used for tlbie(l).
Signed-off-by: Balbir Singh
---
Changelog - Leave the more readable version around
arch/powerpc/include/asm/kvm_boo
On 16/09/16 14:28, Michael Neuling wrote:
> Fred has taken over the cxl maintenance I was doing. This updates the
> MAINTAINERS file to reflect this.
>
> It also removes a duplicate entry in the files covered.
>
> Signed-off-by: Michael Neuling
Reviewed-by: Andrew Donnellan
> CXL (IBM Cohere
On 16/09/16 14:28, Michael Neuling wrote:
Fred has taken over the cxl maintenance I was doing. This updates the
MAINTAINERS file to reflect this.
It also removes a duplicate entry in the files covered.
Signed-off-by: Michael Neuling
Reviewed-by: Andrew Donnellan
CXL (IBM Coherent Accele
User space DTLB miss represent approximatly 90% of TLB misses
so make it the shortest path.
Also remove an unneccessary double jump in FixupDAR
Before this patch, we spend 3.3 TB ticks in the handler for each
user address miss and 3.4 TB ticks for each kernel address miss
After this patch, we sen
When all options are activated, there is not enough space for the
DTLBMiss handlers that handles IMMR area and linear RAM pages in
the exception area once we have added hugepage handling.
So lets move them after .0x2000
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 84
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 8632515..fd5b53d 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/ar
On some CPUs like the 8xx, _PAGE_RW hence _PAGE_WRITE is defined
as 0 and _PAGE_RO has to be set when a page is not writable
_PAGE_RO is defined by default in pte-common.h, however BOOK3S/64
doesn't include that file so _PAGE_RO has to be defined explicitly
in book3s/64/pgtable.h
fixes: a7b9f671f
This serie is a prologue of hugepage implementation on the 8xx.
It some how optimises the DTLBMiss handler while allowing at the
same time to hook the hugepage handling that will be introduced in
a subsequent patch serie.
v1 of those patches was part of a serie identified
"powerpc/8xx: implementat
On 14/09/16 20:40, santhosh wrote:
>
>> Michael Ellerman writes:
>>
>>> On Fri, 2016-19-02 at 05:38:47 UTC, Rashmica Gupta wrote:
Currently on PPC64 changing kernel pagesize from 4K to 64K leaves
FORCE_MAX_ZONEORDER set to 13 - which produces a compile error.
>>> ...
So, upd
Fred has taken over the cxl maintenance I was doing. This updates the
MAINTAINERS file to reflect this.
It also removes a duplicate entry in the files covered.
Signed-off-by: Michael Neuling
---
MAINTAINERS | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAI
Nicholas Piggin writes:
> Use the blacklist macros instead. This allows the linker to move
> exception handler functions close to callers and avoids trampolines in
> larger kernels.
Nice, that's been on my todo list for eva.
Can you do the asm ones too? See _KPROBE() in misc_32/64.S.
cheers
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