Thanks David.
On Tuesday 28 June 2016 09:37 PM, David Laight wrote:
From: Ravi Bangoria
Sent: 28 June 2016 12:37
Powerpc has long list of branch instructions and hardcoding them in table
appears to be error-prone. So, add new function to find instruction
instead of creating table.
Signed-off-
The various calls to establish exception endianness and AIL are
now done from a single point using already established CPU and FW
feature bits to decide what to do.
Signed-off-by: Benjamin Herrenschmidt
---
v2: Add/fix prototypes of exported function, remove "static"
arch/powerpc/include/asm/
On Fri, 2016-24-06 at 04:49:02 UTC, Gavin Shan wrote:
> When calling eeh_rmv_device() in eeh_reset_device() for partial
> hotplug case, @rmv_data instead of its address is the proper
> argument. Otherwise, the stack frame is corrupted when writing
> to @rmv_data (actually its address) in eeh_rmv_de
On Tue, 2016-28-06 at 03:01:04 UTC, Michael Neuling wrote:
> Currently we have 2 segments that are bolted for the kernel linear
> mapping (ie 0xc000... addresses). This is 0 to 1TB and also the kernel
> stacks. Anything accessed outside of these regions may need to be
> faulted in.
...
>
> Signed
On Fri, 2016-17-06 at 04:58:34 UTC, Cyril Bur wrote:
> Userspace can quite legitimately perform an exec() syscall with a
> suspended transaction. exec() does not return to the old process,
...
>
> Fixes: bc2a940 ("powerpc: Hook in new transactional memory code")
> Signed-off-by: Cyril Bur
Applie
Currently the kernel checks to see if the hardware is transactional
memory capable and always enables the MSR_TM bit. The problem with
this is that the TM related SPRs become available to userspace,
requiring them to be switched between processes. It turns out these
SPRs are expensive to read and w
If the kernel disables transactional memory (TM) and userspace still
tries TM related actions (TM instructions or TM SPR accesses) TM aware
hardware will cause the kernel to take a facility unavailable
exception.
Add checks for the exception being caused by illegal TM access in
userspace.
Signed-
Signed-off-by: Cyril Bur
---
.../selftests/powerpc/tm/tm-signal-context-chk.c | 102 +
1 file changed, 102 insertions(+)
create mode 100644 tools/testing/selftests/powerpc/tm/tm-signal-context-chk.c
diff --git a/tools/testing/selftests/powerpc/tm/tm-signal-context-chk.c
b
Currently the MSR TM bit is always set if the hardware is TM capable.
This adds extra overhead as it means the TM SPRS (TFHAR, TEXASR and
TFAIR) must be swapped for each process regardless of if they use TM.
For processes that don't use TM the TM MSR bit can be turned off
allowing the kernel to av
On Wed, 2016-06-29 at 10:54 +0530, Naveen N. Rao wrote:
> On 2016/06/29 10:35AM, Stephen Rothwell wrote:
> >
> > Today's linux-next merge of the powerpc tree got a conflict in:
> >
> > arch/powerpc/Kconfig
> >
> > between commit:
> >
> > 844e3be47693 ("powerpc/bpf/jit: Disable classic BPF J
On 2016/06/29 10:35AM, Stephen Rothwell wrote:
> Hi all,
Hi Stephen,
>
> Today's linux-next merge of the powerpc tree got a conflict in:
>
> arch/powerpc/Kconfig
>
> between commit:
>
> 844e3be47693 ("powerpc/bpf/jit: Disable classic BPF JIT on ppc64le")
Ah, I see that the above commit i
On 24/06/16 19:59, Paul Mackerras wrote:
> On Wed, Jun 15, 2016 at 07:21:05PM +1000, Suraj Jitindar Singh wrote:
>> The struct kvmppc_vcore is a structure used to store various information
>> about a virtual core for a kvm guest. The runnable_threads element of the
>> struct provides a list of all
Implement new character device driver to allow access from user space
to the operator panel display present on IBM Power Systems machines
with FSPs.
This will allow status information to be presented on the display which
is visible to a user.
The driver implements a character buffer which a user
An opal_msg of type OPAL_MSG_ASYNC_COMP contains the return code in the
params[1] struct member. However this isn't intuitive or obvious when
reading the code and requires that a user look at the skiboot
documentation or opal-api.h to verify this.
Add an inline function to get the return code from
Add a binding to Documentation/devicetree/bindings/powerpc/opal
(oppanel-opal.txt) for the operator panel which is present on IBM
Power Systems machines with FSPs.
Signed-off-by: Suraj Jitindar Singh
Acked-by: Rob Herring
Acked-by: Stewart Smith
---
Change Log:
V1 -> V2:
- Nothing
V2
On Tue, 28 Jun 2016 21:58:28 +1000 (AEST)
Michael Ellerman wrote:
> On Tue, 2016-28-06 at 04:40:56 UTC, Suraj Jitindar Singh wrote:
> > An opal_msg of type OPAL_MSG_ASYNC_COMP contains the return code in
> > the params[1] struct member. However this isn't intuitive or
> > obvious when reading the
Hi all,
Today's linux-next merge of the powerpc tree got a conflict in:
arch/powerpc/Kconfig
between commit:
844e3be47693 ("powerpc/bpf/jit: Disable classic BPF JIT on ppc64le")
from Linus' tree and commit:
156d0e290e96 ("powerpc/ebpf/jit: Implement JIT compiler for extended BPF")
from
On Tue, 2016-06-28 at 15:25 +0200, Gerhard Pircher wrote:
> > No we could just add something to early_init_devtree that does clear
> > that bit if it sees the relevant piece of broken HW, it's not the AmigaOne
> > per-se, it's the northbridge right ?
> Does that work for CPU_FTR_NEED_COHERENT, giv
Am Dienstag, 28 Juni 2016, 15:20:55 schrieb Dave Young:
> On 06/27/16 at 04:21pm, Dave Young wrote:
> > Please ignore previous reply, I mistakenly send a broken mail without
> > subject, sorry about it. Resend the reply here.
> >
> > On 06/27/16 at 01:37pm, Thiago Jung Bauermann wrote:
> > > Am Di
Am Donnerstag, 23 Juni 2016, 10:25:06 schrieb Dave Young:
> On 06/22/16 at 08:30pm, Thiago Jung Bauermann wrote:
> > Am Mittwoch, 22 Juni 2016, 18:20:47 schrieb Dave Young:
> > > The patch looks good, but could the subject be more specific?
> > >
> > > For example just like the first sentence of t
> On Jun 23, 2016, at 8:03 AM, Philippe Bergheaud
> wrote:
>
> This adds an afu_driver_ops structure with fetch_event() and
> event_delivered() callbacks. An AFU driver such as cxlflash can fill
> this out and associate it with a context to enable passing custom AFU
> specific events to userspac
The patch
ASoC: fsl_spdif: fix spelling mistake: "receivce" -> "receive"
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hou
On 06/27/16 at 04:21pm, Dave Young wrote:
> Please ignore previous reply, I mistakenly send a broken mail without
> subject, sorry about it. Resend the reply here.
>
> On 06/27/16 at 01:37pm, Thiago Jung Bauermann wrote:
> > Am Dienstag, 28 Juni 2016, 00:19:48 schrieb Dave Young:
> > > On 06/23/16
On 06/27/2016 10:46 PM, Michael Ellerman wrote:
> On Mon, 2016-06-27 at 09:41 -0500, Nathan Fontenot wrote:
>> On 06/24/2016 12:35 AM, Michael Ellerman wrote:
>>> On Mon, 2016-06-20 at 21:14 -0500, Nathan Fontenot wrote:
On 06/20/2016 07:57 PM, Michael Ellerman wrote:
> On Mon, 2016-06-20
From: Ravi Bangoria
> Sent: 28 June 2016 12:37
>
> Powerpc has long list of branch instructions and hardcoding them in table
> appears to be error-prone. So, add new function to find instruction
> instead of creating table.
>
> Signed-off-by: Naveen N. Rao
> Signed-off-by: Ravi Bangoria
> ---
>
On Tue, Jun 28, 2016 at 01:47:59PM +0100, Colin King wrote:
> From: Colin Ian King
Please fix things so that your mail configuration matches your git
configuration, it makes things harder to review since it looks like
you've got a non-author signoff with a missing signed off by from
someone.
si
Darren Stevens writes:
> Hello All,
>
> commit d6a9996e84ac4beb7713e9485f4563e100a9b03e
> powerpc/mm: vmalloc abstraction in preparation for radix
>
> This commit introduced variables for some linux kernel addresses that had
> before
> been constants, unfortunately this stopped Pa
Michael Ellerman writes:
> On Thu, 2016-06-23 at 14:37 -0500, Reza Arbab wrote:
>> On Thu, Jun 23, 2016 at 10:47:20PM +0530, Aneesh Kumar K.V wrote:
>> > Reza Arbab writes:
>> > > These functions are making direct calls to the hash table APIs,
>> > > leading to a BUG() on systems using radix.
>>
On Tue, 2016-06-28 at 14:01 +0200, Benjamin Herrenschmidt wrote:
> On Tue, 2016-06-28 at 13:42 +0200, Gerhard Pircher wrote:
> > The question is, if a compile time option that simply clear ?s
> > CPU_FTR_NEED_COHERENT after identify_cpu() would be acceptable. And
> > then I still wonder why KVM nee
From: Colin Ian King
trivial fix to spelling mistake in dev_err message
Signed-off-by: Colin Ian King
---
sound/soc/fsl/fsl_spdif.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index 151849f..beec793 100644
--- a/soun
On Wed, 2016-22-06 at 07:23:07 UTC, Benjamin Herrenschmidt wrote:
> If a PHB has no I/O space, there's no need to make it look like
> something bad happened, a pr_debug() is plenty enough since this
> is the case of all our modern POWER chips.
>
> Signed-off-by: Benjamin Herrenschmidt
Applied to
On Wed, 2016-22-06 at 16:25:02 UTC, "Naveen N. Rao" wrote:
> The existing LI32() macro can sometimes result in a sign-extended 32-bit
> load that does not clear the top 32-bits properly. As an example,
> loading 0x7fff results in the register containing
> 0x7fff. While this does not
On Wed, 2016-08-06 at 16:54:27 UTC, "Shreyas B. Prabhu" wrote:
> pnv_init_idle_states discovers supported idle states from the
> device tree and does the required initialization. Set power_save
> function pointer only after this initialization is done
>
> Reviewed-by: Gautham R. Shenoy
> Signed-o
On Tue, 2016-06-28 at 13:42 +0200, Gerhard Pircher wrote:
> The question is, if a compile time option that simply clear ?s
> CPU_FTR_NEED_COHERENT after identify_cpu() would be acceptable. And
> then I still wonder why KVM needs its own similar fix to work on the
> AmigaOne. I specifically had to r
On Tue, 2016-28-06 at 04:40:56 UTC, Suraj Jitindar Singh wrote:
> An opal_msg of type OPAL_MSG_ASYNC_COMP contains the return code in the
> params[1] struct member. However this isn't intuitive or obvious when
> reading the code and requires that a user look at the skiboot
> documentation or opal-a
On Tue, 2016-06-28 at 17:19 +0530, Aneesh Kumar K.V wrote:
> If we can do feature fixup early. Then this patch series become
> simpler.
>
> https://lkml.kernel.org/r/1465887288-12952-1-git-send-email-aneesh.ku
> m...@linux.vnet.ibm.com
>
> ie, we can now start using cpu_has_feature/mmu_has_featur
On Tue, 2016-06-28 at 21:37 +1000, Michael Ellerman wrote:
> Yeah Ben already told me.
>
> I don't know which will go in first yet, this has had zero revisions and zero
> reviews so it might not go in straight away ;)
The point was that patch could go in independently of the rest but I really
don
Benjamin Herrenschmidt writes:
> On Tue, 2016-06-28 at 16:35 +0530, Aneesh Kumar K.V wrote:
>> Why not move it immediately after we finish all the device tress
>> scan.
>
> Do you need it in early_init_mmu ? The important thing is to have it
> done before we *turn on* the MMU but yeah, there's no
On Mon, 2016-06-27 at 23:40 +0200, Benjamin Herrenschmidt wrote:
> On Mon, 2016-06-27 at 22:42 +0200, Gerhard Pircher wrote:
> > This patch series reminds me of a long-standing issue with the
> > AmigaOne platform code, which would have to clear the coherence
> > (M) flag for every memory mapping t
From: "Naveen N. Rao"
Powerpc has long list of branch instructions and hardcoding them in table
appears to be error-prone. So, add new function to find instruction
instead of creating table.
Signed-off-by: Naveen N. Rao
Signed-off-by: Ravi Bangoria
---
tools/perf/util/annotate.c | 64
On Tue, 2016-06-28 at 14:18 +1000, Michael Neuling wrote:
> mpe,
>
> Just flagging this as going to conflict with Shreyas' stop instruction
> patch series. It's relatively easy to fix so you can do it manually.
>
> Alternatively you could take this one patch now and get Shreyas to rebase.
Yeah
Define macro for each arch name and use them instead of using arch
name as string.
Signed-off-by: Ravi Bangoria
---
tools/perf/arch/common.c | 36 ++--
tools/perf/arch/common.h | 11 +++
tools/perf/util/annotate.c | 10 +
Change current data structures and function to enable cross arch
annotate.
Current implementation does not contain logic of record on one arch
and annotate on other. This remote annotate is partially possible
with current implementation for x86 (or may be arm as well) only.
But, to make remote ann
Add Utility function to fetch 'arch' from 'evsel'. (evsel->env->arch)
Signed-off-by: Ravi Bangoria
---
tools/perf/util/evsel.c | 7 +++
tools/perf/util/evsel.h | 2 ++
2 files changed, 9 insertions(+)
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index 1d8f2bb..0fea724 1006
Perf can currently only support code navigation (branches and calls) in
annotate when run on the same architecture where perf.data was recorded.
But cross arch annotate is not supported.
This patchset enables cross arch annotate. Currently I've used x86
and arm instructions which are already avail
On Thu, 2016-06-23 at 14:37 -0500, Reza Arbab wrote:
> On Thu, Jun 23, 2016 at 10:47:20PM +0530, Aneesh Kumar K.V wrote:
> > Reza Arbab writes:
> > > These functions are making direct calls to the hash table APIs,
> > > leading to a BUG() on systems using radix.
> > >
> > > Switch them to the vme
On Tue, 2016-06-28 at 16:35 +0530, Aneesh Kumar K.V wrote:
> Why not move it immediately after we finish all the device tress
> scan.
Do you need it in early_init_mmu ? The important thing is to have it
done before we *turn on* the MMU but yeah, there's no big deal
moving it even further up I thin
On Tue, 2016-06-28 at 16:15 +0530, Aneesh Kumar K.V wrote:
> Michael Ellerman writes:
> > diff --git a/arch/powerpc/include/asm/pgtable.h
> > b/arch/powerpc/include/asm/pgtable.h
> > index ee09e99097f0..651848039dc4 100644
> > --- a/arch/powerpc/include/asm/pgtable.h
> > +++ b/arch/powerpc/includ
Benjamin Herrenschmidt writes:
> Make it part of early_setup() as we really want the feature fixups
> to be applied before we turn on the MMU since they can have an impact
> on the various assembly path related to MMU management and interrupts.
>
> This makes 64-bit match what 32-bit does.
>
> Si
Hi Darren,
On Sun, 2016-26-06 at 17:42:11 UTC, Darren Stevens wrote:
> Hello All,
>
> commit d6a9996e84ac4beb7713e9485f4563e100a9b03e
> powerpc/mm: vmalloc abstraction in preparation for radix
>
> This commit introduced variables for some linux kernel addresses that had
> before
>
Michael Ellerman writes:
> The check for !arch_irqs_disabled() in find_linux_pte_or_hugepte() is a
> debugging aid, and needn't be enabled for production builds.
>
> Switch it to a VM_WARN_ONCE(), which is compiled out when
> CONFIG_DEBUG_VM=n.
>
> Signed-off-by: Michael Ellerman
> ---
> arch/p
An over-committed guest with more vCPUs than pCPUs has a heavy overload in
osq_lock().
This is because vCPU A hold the osq lock and yield out, vCPU B wait per_cpu
node->locked to be set. IOW, vCPU B wait vCPU A to run and unlock the osq
lock.
Kernel has an interface bool vcpu_is_preempted(int cpu
An over-committed guest with more vCPUs than pCPUs has a heavy overload in
the two spin_on_owner. This blames on the lock holder preemption issue.
Kernel has an interface bool vcpu_is_preempted(int cpu) to see if a vCPU is
currently running or not. So break the spin loops on true condition.
test-
This is to fix some lock holder preemption issues. Some other locks
implementation do a spin loop before acquiring the lock itself. Currently
kernel has an interface of bool vcpu_is_preempted(int cpu). It take the cpu
as parameter and return true if the cpu is preempted. Then kernel can break
the s
This patch support to fix lock holder preemption issue.
For kernel users, we could use bool vcpu_is_preempted(int cpu) to detech if
one vcpu is preempted or not.
The default implementation is a macro defined by false. So compiler can
wrap it out if arch dose not support such vcpu pteempted check.
change fomr v1:
a simplier definition of default vcpu_is_preempted
skip mahcine type check on ppc, and add config. remove dedicated macro.
add one patch to drop overload of rwsem_spin_on_owner and
mutex_spin_on_owner.
add more comments
thanks boqun and Pete
On Tue, 2016-06-28 at 08:06 +0100, David Binderman wrote:
>
> I don't know the code, but given that insn is unsigned long and so
> can go
> past 32 bits, using a cast to unsigned int might throw away the
> possibly important
> upper bits.
our instructions are only ever 32-bits. That xmon code is
On 2016年06月28日 15:00, Heiko Carstens wrote:
On Mon, Jun 27, 2016 at 04:00:43PM +0200, Peter Zijlstra wrote:
On Mon, Jun 27, 2016 at 01:41:28PM -0400, Pan Xinhui wrote:
+++ b/include/linux/sched.h
@@ -3293,6 +3293,15 @@ static inline void set_task_cpu(struct task_struct *p,
unsigned int cpu)
Michael Ellerman wrote:
On Fri, 2016-24-06 at 06:47:07 UTC, Philippe Bergheaud wrote:
From: Michael Neuling
This provides AFU drivers a means to associate private data with a cxl
context. This is particularly intended for make the new callbacks for
driver specific events easier for AFU driver
On Thu, Jun 23, 2016 at 11:19:27AM +0530, Madhavan Srinivasan wrote:
SNIP
>
> Changelog v1:
> 1)updated commit message and patch subject
> 2)Add the fix to print_sample_iregs() in builtin-script.c
>
> tools/include/linux/bitmap.h | 2 ++
> tools/lib/bitmap.c | 18 ++
On Fri, 2016-24-06 at 06:47:07 UTC, Philippe Bergheaud wrote:
> From: Michael Neuling
>
> This provides AFU drivers a means to associate private data with a cxl
> context. This is particularly intended for make the new callbacks for
> driver specific events easier for AFU drivers to use, as they
On 24/06/16 16:47, Philippe Bergheaud wrote:
From: Michael Neuling
This provides AFU drivers a means to associate private data with a cxl
context. This is particularly intended for make the new callbacks for
driver specific events easier for AFU drivers to use, as they can easily
get back to an
On Tue, Jun 28, 2016 at 08:06:56AM +0100, David Binderman wrote:
> I think you can also get a similar warning if you tweek the gcc compiler
> warning
> flags. -Wformat=2 maybe.
-Wformat=1 (which is enabled by -Wall) already warns for this.
warning: format '%x' expects argument of type 'unsigned
On Tue, 2016-06-28 at 08:06 +0100, David Binderman wrote:
> On Tue, Jun 28, 2016 at 5:08 AM, Michael Ellerman wrote:
> > What config / toolchain are you using? I've never seen these.
>
> A static analyser for C & C++ called cppcheck. Available from sourceforge.
>
> I think you can also get a sim
Hello there,
On Tue, Jun 28, 2016 at 5:08 AM, Michael Ellerman wrote:
> What config / toolchain are you using? I've never seen these.
A static analyser for C & C++ called cppcheck. Available from sourceforge.
I think you can also get a similar warning if you tweek the gcc compiler warning
flags
On Mon, Jun 27, 2016 at 04:00:43PM +0200, Peter Zijlstra wrote:
> On Mon, Jun 27, 2016 at 01:41:28PM -0400, Pan Xinhui wrote:
> > +++ b/include/linux/sched.h
> > @@ -3293,6 +3293,15 @@ static inline void set_task_cpu(struct task_struct
> > *p, unsigned int cpu)
> >
> > #endif /* CONFIG_SMP */
>
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