On Thu, 2016-05-05 at 15:23:19 UTC, "Naveen N. Rao" wrote:
> Generalize existing macros to serve the purpose.
>
> Cc: Wang Nan
> Cc: Arnaldo Carvalho de Melo
> Cc: Masami Hiramatsu
> Cc: Ian Munsie
> Cc: Michael Ellerman
> Signed-off-by: Naveen N. Rao
> ---
> With this patch:
> # ./perf
On Fri, 2016-06-05 at 11:51:08 UTC, Hari Bathini wrote:
> Kernel parameter 'nr_cpus' can be used to limit the maximum number
> of processors that an SMP kernel could support. This patch extends
> this to fadump by introducing 'fadump_nr_cpus' parameter that can
> help in booting fadump kernel on a
On Fri, 2016-06-05 at 11:50:37 UTC, Hari Bathini wrote:
> Currently, memory for fadump can be specified with fadump_reserve_mem=size,
> where only a fixed size can be specified. This patch tries to extend this
> syntax to support conditional reservation based on memory size, with the
> below syntax
On Fri, 6 May 2016 16:35:38 +1000
Alexey Kardashevskiy wrote:
> On 05/06/2016 01:05 AM, Alex Williamson wrote:
> > On Thu, 5 May 2016 12:15:46 +
> > "Tian, Kevin" wrote:
> >
> >>> From: Yongji Xie [mailto:xyj...@linux.vnet.ibm.com]
> >>> Sent: Thursday, May 05, 2016 7:43 PM
> >>>
> >>> Hi
On Thu, May 5, 2016 at 7:28 PM, Gavin Shan wrote:
> On Thu, May 05, 2016 at 12:04:49PM -0500, Rob Herring wrote:
>>On Tue, May 3, 2016 at 8:22 AM, Gavin Shan wrote:
>>> This adds standalone driver to support PCI hotplug for PowerPC PowerNV
>>> platform that runs on top of skiboot firmware. The fi
On Fri, May 06, 2016 at 01:33:01PM +0200, Petr Mladek wrote:
> On Thu 2016-04-28 15:44:48, Josh Poimboeuf wrote:
> > diff --git a/kernel/livepatch/patch.c b/kernel/livepatch/patch.c
> > index 782fbb5..b3b8639 100644
> > --- a/kernel/livepatch/patch.c
> > +++ b/kernel/livepatch/patch.c
> > @@ -29,6
Getting the following at shutdown with Kernel 4.6-rc's on Sam460ex
Canyonlands board .
Regards
Julian
[ 1533.722779] Unable to handle kernel paging request for data at
address 0x0128
[ 1533.744309] Faulting instruction address: 0xc026d3c8
[ 1535.763583] Oops: Kernel access of bad area, s
On Thu, May 05, 2016 at 01:57:01PM +0200, Petr Mladek wrote:
> I have missed that the two commands are called with preemption
> disabled. So, I had the following crazy scenario in mind:
>
>
> CPU0 CPU1
>
> klp_enable_patch()
>
> klp_target_state = KLP_PATCHED;
>
>
Kernel parameter 'nr_cpus' can be used to limit the maximum number
of processors that an SMP kernel could support. This patch extends
this to fadump by introducing 'fadump_nr_cpus' parameter that can
help in booting fadump kernel on a lower memory footprint.
Suggested-by: Mahesh Salgaonkar
Signed
Currently, memory for fadump can be specified with fadump_reserve_mem=size,
where only a fixed size can be specified. This patch tries to extend this
syntax to support conditional reservation based on memory size, with the
below syntax:
fadump_reserve_mem=:[,:,...]
This syntax helps using
When boot memory size for fadump is not specified, memory is reserved
for fadump based on system RAM size. As the system RAM size increases,
the memory reserved for fadump increases as well. This patch sets an
upper limit on the memory reserved for fadump, to avoid reserving
excess memory.
Signed-
On Tue, 2016-02-16 at 14:29 +0530, Anshuman Khandual wrote:
> This patch series adds twelve new ELF core note sections which can
> be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for accessing
> various transactional memory and other miscellaneous debug register sets on
> pow
On Thu 2016-04-28 15:44:48, Josh Poimboeuf wrote:
> diff --git a/kernel/livepatch/patch.c b/kernel/livepatch/patch.c
> index 782fbb5..b3b8639 100644
> --- a/kernel/livepatch/patch.c
> +++ b/kernel/livepatch/patch.c
> @@ -29,6 +29,7 @@
> #include
> #include
> #include "patch.h"
> +#include "tra
On Fri, May 06, 2016 at 05:17:25PM +1000, Alexey Kardashevskiy wrote:
>On 05/03/2016 11:22 PM, Gavin Shan wrote:
>>Each PHB maintains an array helping to translate 2-bytes Request
>>ID (RID) to PE# with the assumption that PE# takes one byte, meaning
>>that we can't have more than 256 PEs. However,
On 2016/05/05 05:32PM, Naveen N Rao wrote:
> On 2016/02/29 05:53PM, Cyril Bur wrote:
> > Cover-letter for V1 of the series is at
> > https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-November/136350.html
> >
> > Cover-letter for V2 of the series is at
> > https://lists.ozlabs.org/pipermail/linu
Hi Linus,
Please pull one powerpc fix for 4.6:
The following changes since commit d701cca6744fe0d67c86346dcfc9b128b17b5045:
powerpc: wire up preadv2 and pwritev2 syscalls (2016-04-27 16:47:55 +1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/power
From: Ian Munsie
cxl devices typically access memory using an MMU in much the same way as
the CPU, and each context includes a state register much like the MSR in
the CPU. Like the CPU, the state register includes a bit to enable
relocation, which we currently always enable.
In some cases, it ma
Sure thing, that actually simplifies things a great deal. Testing now
and will resend shortly :)
-Ian
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On 05/03/2016 11:22 PM, Gavin Shan wrote:
Each PHB maintains an array helping to translate 2-bytes Request
ID (RID) to PE# with the assumption that PE# takes one byte, meaning
that we can't have more than 256 PEs. However, pci_dn->pe_number
already had 4-bytes for the PE#.
Can you possibly have
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