On Thu, 2016-04-21 at 09:30 +0530, Madhavan Srinivasan wrote:
> @@ -488,17 +489,17 @@ static int power8_compute_mmcr(u64 event[], int n_ev,
>
> /* Table of alternatives, sorted by column 0 */
> static const unsigned int event_alternatives[][MAX_ALT] = {
> - { 0x10134, 0x301e2 }, /
On Thu, 2016-04-21 at 14:15 +1000, Balbir Singh wrote:
>
> On 21/04/16 13:37, Michael Ellerman wrote:
> > Testing done by Paul Mackerras has shown that with a modern compiler
> > there is no negative effect on code generation from enabling
> > STRICT_MM_TYPECHECKS.
> >
> > So remove the option,
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> For those pte accessors, that operate on a different set of pte bits
> between hash/radix, we add a generic variant that does a conditional
> to hash linux or radix variant.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
Looks good!
Balbir
_
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> In this patch we add the radix Kconfig and conditional check.
> radix_enabled is written to always return 0 here. Once we have
> all needed radix changes added, we will update this to mmu_feature
> check.
>
> We need to addt this early so that we can
On 21/04/16 13:37, Michael Ellerman wrote:
> Testing done by Paul Mackerras has shown that with a modern compiler
> there is no negative effect on code generation from enabling
> STRICT_MM_TYPECHECKS.
>
> So remove the option, and always use the strict type definitions.
>
Should we wait for An
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> This add PowerISA 3.0 specific pte defines. We share most of the
> details with hash linux page table format. This patch indicate only
> things where we differ
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/include/asm/book3s/64/pgtable.h
Minor cleanup patch to replace the raw event hex values in
power8-pmu.c with #def.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/power8-events-list.h | 42 ++
arch/powerpc/perf/power8-pmu.c | 41 +
2 files changed
Testing done by Paul Mackerras has shown that with a modern compiler
there is no negative effect on code generation from enabling
STRICT_MM_TYPECHECKS.
So remove the option, and always use the strict type definitions.
Signed-off-by: Michael Ellerman
---
arch/powerpc/Kconfig.debug
On 04/21/2016 10:21 AM, Gavin Shan wrote:
On Fri, Apr 08, 2016 at 04:36:44PM +1000, Alexey Kardashevskiy wrote:
When SRIOV is disabled, the existing code presumes there is no
virtual function (VF) in use and destroys all associated PEs.
However it is possible to get into the situation when the u
On 04/21/2016 10:02 AM, Gavin Shan wrote:
On Fri, Apr 08, 2016 at 04:36:43PM +1000, Alexey Kardashevskiy wrote:
IBM PPC IOMMU API users always set IOMMU data and IOMMU release callback
to an IOMMU group. At the moment the callback clears one pointer in
iommu_table_group and that's it.
The platf
On Fri, Apr 08, 2016 at 04:36:44PM +1000, Alexey Kardashevskiy wrote:
>When SRIOV is disabled, the existing code presumes there is no
>virtual function (VF) in use and destroys all associated PEs.
>However it is possible to get into the situation when the user
>activated SRIOV disabling while a VF
On Fri, Apr 08, 2016 at 04:36:43PM +1000, Alexey Kardashevskiy wrote:
>IBM PPC IOMMU API users always set IOMMU data and IOMMU release callback
>to an IOMMU group. At the moment the callback clears one pointer in
>iommu_table_group and that's it.
>
>The platform code calls iommu_group_put() and cou
On Wed, Apr 20, 2016 at 10:32 AM, Geert Uytterhoeven
wrote:
> Hi all,
>
> This patch series fixes misspellings of various standard DT properties
> in DT binding documentation, DTS files, and error messages.
> While most of these are harmless, some of them may cause hard-to-debug
> failures
On Wed, Apr 20, 2016 at 10:32 AM, Geert Uytterhoeven
wrote:
> Signed-off-by: Geert Uytterhoeven
> ---
> arch/arm/boot/dts/omap36xx.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
> index ce1e242d4dc07
On Wed, 2016-04-20 at 12:02 +0200, Alessio Igor Bogani wrote:
> Add support for the Artesyn MVME7100 Single Board Computer.
>
> The MVME7100 is a 6U form factor VME64 computer with:
>
> - A two e600 cores Freescale MPC8641D CPU
> - 2 GB of DDR2 onboard memory
> - Four Gigabit Ethernet
> From: Aneesh Kumar K.V [mailto:aneesh.ku...@linux.vnet.ibm.com]
> Sent: Wednesday, April 20, 2016 3:58 AM
> Subject: [PATCH V2] powerpc/infiniband: Use cache inhibitted and guarded
> mapping on powerpc
>
Doug, can you fix up the summary to git the spelling error and
powerpc/infiniband: -> IB/
Signed-off-by: Geert Uytterhoeven
---
Documentation/devicetree/booting-without-of.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/booting-without-of.txt
b/Documentation/devicetree/booting-without-of.txt
index 3f1437fbca6b49f3..5bcea91c0cc65af2 100
Hi all,
This patch series fixes misspellings of various standard DT properties
in DT binding documentation, DTS files, and error messages.
While most of these are harmless, some of them may cause hard-to-debug
failures.
Please apply where appropriate.
Thanks!
P.S. I used the following t
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/stih407-pinctrl.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi
b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index a538ae52d32b7cbb..7517d373e10836ff 100644
--- a/arch/arm/boot/dts
Signed-off-by: Geert Uytterhoeven
---
Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt
b/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt
index 00944a05
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/omap36xx.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index ce1e242d4dc07ea8..8b797915300894d8 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/a
Signed-off-by: Geert Uytterhoeven
---
Documentation/devicetree/bindings/rtc/sa1100-rtc.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
b/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
index 0cda19ad4859c541..968ac
Signed-off-by: Geert Uytterhoeven
---
.../devicetree/bindings/input/touchscreen/brcm,iproc-touchscreen.txt| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/input/touchscreen/brcm,iproc-touchscreen.txt
b/Documentation/devicetree/bindings/i
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/omap5-board-common.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi
b/arch/arm/boot/dts/omap5-board-common.dtsi
index 902657d6713b073d..cdd144acbd3fbb53 100644
--- a/arch/arm
Signed-off-by: Geert Uytterhoeven
---
arch/powerpc/boot/dts/acadia.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/acadia.dts b/arch/powerpc/boot/dts/acadia.dts
index 57291f61ffe7021a..86266159521edac2 100644
--- a/arch/powerpc/boot/dts/acadia.dts
+++
Signed-off-by: Geert Uytterhoeven
---
.../devicetree/bindings/regulator/ti-abb-regulator.txt | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
b/Documentation/devicetree/bindings/regulator/ti-ab
Signed-off-by: Geert Uytterhoeven
---
Documentation/devicetree/bindings/pci/hisilicon-pcie.txt | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
inde
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/omap5-cm-t54.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts
b/arch/arm/boot/dts/omap5-cm-t54.dts
index ecc591dc0778ddbf..467291d71e96e5fe 100644
--- a/arch/arm/boot/dts/omap5-cm-t5
Signed-off-by: Geert Uytterhoeven
---
Documentation/devicetree/bindings/sound/davinci-mcbsp.txt | 2 +-
drivers/dma/bcm2835-dma.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt
b/Doc
Signed-off-by: Geert Uytterhoeven
---
Documentation/devicetree/bindings/sram/sram.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sram/sram.txt
b/Documentation/devicetree/bindings/sram/sram.txt
index 227e3a341af1e2b5..add48f09015e212e 100
Signed-off-by: Geert Uytterhoeven
---
arch/arm64/boot/dts/lg/lg1312.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi
b/arch/arm64/boot/dts/lg/lg1312.dtsi
index 3a4e9a2ab3130106..1d625c5bb4bfc503 100644
--- a/arch/arm64/boot/dts/lg/lg1312
On 20/04/2016 at 17:32:18 +0200, Geert Uytterhoeven wrote :
> Signed-off-by: Geert Uytterhoeven
> ---
> Documentation/devicetree/bindings/rtc/sa1100-rtc.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied, thanks.
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel an
On Wed, Apr 20, 2016 at 05:32:14PM +0200, Geert Uytterhoeven wrote:
> Signed-off-by: Geert Uytterhoeven
Applied, thank you.
> ---
> .../devicetree/bindings/input/touchscreen/brcm,iproc-touchscreen.txt| 2
> +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
> a/Documentati
Tested-by: Manoj Kumar
On 4/19/2016 11:34 AM, Frederic Barrat wrote:
PSL designers recommend a larger value for the mmio hang pulse, 256 us
instead of 1 us. The CAIA architecture states that it needs to be
smaller than 1/2 of the RTOS timeout set in the PHB for outbound
non-posted transactions,
Akshay Adiga writes:
> Iozone results show fairly consistent performance boost.
> YCSB on redis shows improved Max latencies in most cases.
What about power consumption?
> Iozone write/rewite test were made with filesizes 200704Kb and 401408Kb
> with different record sizes . The following table
Received privately:
Tested-by: Frank Haverkamp
Le 19/04/2016 18:34, Frederic Barrat a écrit :
PSL designers recommend a larger value for the mmio hang pulse, 256 us
instead of 1 us. The CAIA architecture states that it needs to be
smaller than 1/2 of the RTOS timeout set in the PHB for outbou
On Wed, Apr 20, 2016 at 5:32 PM, Geert Uytterhoeven
wrote:
> This patch series fixes misspellings of various standard DT properties
> in DT binding documentation, DTS files, and error messages.
BTW, this is against next-20160420.
Gr{oetje,eeting}s,
Geert
--
On Wed, Apr 20, 2016 at 09:24:00PM +0800, Pan Xinhui wrote:
> +#define __XCHG_GEN(cmp, type, sfx, skip, v) \
> +static __always_inline unsigned long \
> +__cmpxchg_u32##sfx(v unsigned int *p, unsigned long old, \
> +
On Thu, Apr 14, 2016 at 01:36:33PM +1000, Alexey Kardashevskiy wrote:
>On 04/14/2016 09:54 AM, Gavin Shan wrote:
>>On Wed, Apr 13, 2016 at 06:29:42PM +1000, Alexey Kardashevskiy wrote:
>>>On 02/17/2016 02:43 PM, Gavin Shan wrote:
Currently, there is one macro (TCE32_TABLE_SIZE) representing the
On Mon 2016-04-04 11:38:19, Petr Mladek wrote:
> On Mon 2016-04-04 13:49:28, Sergey Senozhatsky wrote:
> > Hello,
> >
> > On (03/30/16 17:53), Petr Mladek wrote:
> > > +/*
> > > + * Flush data from the associated per_CPU buffer. The function
> > > + * can be called either via IRQ work or independe
From: Pan Xinhui
Implement xchg{u8,u16}{local,relaxed}, and
cmpxchg{u8,u16}{,local,acquire,relaxed}.
It works on all ppc.
The basic idea is from commit 3226aad81aa6 ("sh: support 1 and 2 byte xchg")
Suggested-by: Peter Zijlstra (Intel)
Signed-off-by: Pan Xinhui
---
change from v2:
in
Em Wed, Apr 20, 2016 at 02:55:58PM +1000, Michael Ellerman escreveu:
> On Wed, 2016-04-20 at 00:57 -0300, Arnaldo Carvalho de Melo wrote:
> > Em Mon, Apr 18, 2016 at 03:17:11PM +0530, Anju T escreveu:
> > > On Saturday 20 February 2016 10:32 AM, Anju T wrote:
> > > > tools/perf/arch/powerpc/includ
On Wed, 2016-04-20 at 12:59 +1000, Michael Ellerman wrote:
> On Sat, 2016-09-04 at 06:14:04 UTC, "Aneesh Kumar K.V" wrote:
> > We can depend on ibm,pa-features to enable/disable radix. This gives us
> > a nice way to test p9 hash config, by changing device tree property.
>
> I think we might wan
Thank you for your comment. I'll change it according to the GPIO binding
document.
Thanks,
Chenhui
From: Yang-Leo Li
Sent: Saturday, April 16, 2016 12:47 AM
To: Chenhui Zhao; linuxppc-dev@lists.ozlabs.org; o...@buserror.net
Cc: Chenhui Zhao; Zhengxiong J
Provide clocks property instead of clock-frequency for QorIQ eSDHC
dts node to adapt to the new clocking model, so that the driver
could get clock value by the common clk API and the u-boot could
remove the clock fixup.
Signed-off-by: Yangbo Lu
---
arch/powerpc/boot/dts/fsl/qoriq-esdhc-0.dtsi |
Get the sdhc clock through the common clk APIs. If the APIs fail, try
to get the clock through 'clock-frequency' property. We could remove
the clock fixup in u-boot by adding the common clk APIs support.
Signed-off-by: Yangbo Lu
---
drivers/mmc/host/sdhci-pltfm.c | 8 +++-
1 file changed, 7
Add support for the Artesyn MVME7100 Single Board Computer.
The MVME7100 is a 6U form factor VME64 computer with:
- A two e600 cores Freescale MPC8641D CPU
- 2 GB of DDR2 onboard memory
- Four Gigabit Ethernets
- Five 16550 compatible UARTs
- One USB 2.0 port
- Two PCI/PCI
On Mon, Apr 18, 2016 at 01:42:49PM +0200, Christian Lamparter wrote:
>
> what else I fixed in v1->v2:
> - added a check to test trng device's status state with
>of_device_is_available.
> - if the hwrng device registration failed, the flag which
>enables the trng was left enabled (note: t
On 20-04-16, 15:02, Shilpasri G Bhat wrote:
> commit 735366fc4077 ("cpufreq: powernv: Call throttle_check() on
> receiving OCC_THROTTLE") used cpumask_of_node() as the chip mask. But
> this mask contains only online cpus. This breaks a setup where cpufreq
> is initialized with few offline cores and
commit 735366fc4077 ("cpufreq: powernv: Call throttle_check() on
receiving OCC_THROTTLE") used cpumask_of_node() as the chip mask. But
this mask contains only online cpus. This breaks a setup where cpufreq
is initialized with few offline cores and made online later. So this
patch fixes this bug by
This replaces:
- "select ARCH_REQUIRE_GPIOLIB" with "select GPIOLIB" as this can
now be selected directly.
- "select ARCH_WANT_OPTIONAL_GPIOLIB" with no dependency: GPIOLIB
is now selectable by everyone, so we need not declare our
intent to select it.
When ordering the symbols the followin
Michael Ellerman writes:
> On Sat, 2016-09-04 at 06:14:04 UTC, "Aneesh Kumar K.V" wrote:
>> We can depend on ibm,pa-features to enable/disable radix. This gives us
>> a nice way to test p9 hash config, by changing device tree property.
>
> I think we might want to be more careful here.
>
> You se
Signed-off-by: Alessio Igor Bogani
---
Please note that this patch replaces completely
https://lists.ozlabs.org/pipermail/linuxppc-dev/2016-April/141785.html
arch/powerpc/boot/dts/fsl/gef_ppc9a.dts| 4
arch/powerpc/boot/dts/fsl/gef_sbc310.dts | 22 -
arch/
Also the wrong `~` operation resulted in wrong access check as explained
below.
The current code will set _PAGE_USER to the access flags for any
fault address because ~ operation will be true for all address we take
a fault on. But setting _PAGE_USER also means that the fault will be
handled only
The driver was requesting for a writethrough mapping. But with thoses
flags we will end up with a SAO mapping because we now have memory
conherence always enabled. ie, the existing mapping will end up with
a WIMG value 0b1110 which is Strong Access Order.
Update this to use cache inhibitted guarde
Michael Ellerman writes:
> On Wed, 2016-04-13 at 08:12 +0530, Aneesh Kumar K.V wrote:
>> "Aneesh Kumar K.V" writes:
>> > Also note that the `~` operation is wrong.
>> >
>> > Cc: Frederic Barrat
>> > Cc: Andrew Donnellan
>> > Acked-by: Ian Munsie
>> > Signed-off-by: Aneesh Kumar K.V
>> > ---
Michael Ellerman writes:
> On Sat, 2016-09-04 at 06:12:58 UTC, "Aneesh Kumar K.V" wrote:
>> if it is a hugetlb address return without calling __flush_tlb_page.
>
> Why?
>
> cheers
Because flush_hugetlb_page will do the necessary flush
-aneesh
___
Lin
57 matches
Mail list logo
