On 02/17/2016 02:43 PM, Gavin Shan wrote:
The original implementation of pnv_ioda_setup_pe_seg() configures
IO and M32 segments by separate logics, which can be merged by
by caching @segmap, @seg_size, @win in advance. This shouldn't
cause any behavioural changes.
>
Signed-off-by: Gavin Shan
-
If ->get_char() returns a negative error code and that can mean that
"ch" is uninitialized. The callers of this function expect NO_POLL_CHAR
on error so let's return that.
Signed-off-by: Dan Carpenter
diff --git a/drivers/tty/hvc/hvc_console.c b/drivers/tty/hvc/hvc_console.c
index e46d628..3257
On 02/17/2016 02:43 PM, Gavin Shan wrote:
There are two arrays for IO and M32 segment maps on every PHB.
The index of the arrays are segment number and the value stored
in the corresponding element is PE number, indicating the segment
is assigned to the PE. Initially, all elements in those two ar
On 02/17/2016 02:43 PM, Gavin Shan wrote:
This renames the fields related to PE number in "struct pnv_phb"
for better reflecting of their usages as Alexey suggested. No
logical changes introduced.
Signed-off-by: Gavin Shan
Reviewed-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/po
On 02/17/2016 02:43 PM, Gavin Shan wrote:
This moves those fields in struct pnv_phb that are related to PE
allocation around. No logical change.
Signed-off-by: Gavin Shan
Reviewed-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci.h | 7 +++
1 file changed, 3 inserti
On 02/17/2016 02:43 PM, Gavin Shan wrote:
This drops struct pnv_phb::bdfn_to_pe() as nobody uses it.
Signed-off-by: Gavin Shan
Reviewed-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 9 -
arch/powerpc/platforms/powernv/pci.h | 1 -
2 files chan
On 02/17/2016 02:43 PM, Gavin Shan wrote:
This overrides pcibios_setup_bridge() that is called to update PCI
bridge windows when PCI resource assignment is completed, to assign
PE and setup various (resource) mapping for the PE in subsequent
patches.
Signed-off-by: Gavin Shan
Reviewed-by: A
On 02/17/2016 02:43 PM, Gavin Shan wrote:
Each PHB has one instance of "struct pci_controller_ops", which
includes various callbacks called by PCI subsystem. In the definition
of this struct, some callbacks have explicit names for its arguments,
but the left don't have.
This adds all explicit na
On Mon, 2016-04-11 at 03:32 -0300, Edjunior Barbosa Machado wrote:
> Hi Michael, Anshuman,
>
> I've managed to implement the GDB support for the new regsets and test
> on Power8 (BE and LE).
Great work thanks!
> The following is an example of GDB 'info
> registers all' partial output showing the
On Mon, 2016-04-11 at 09:40 +0200, Laurent Dufour wrote:
> On 07/04/2016 23:49, Michael Ellerman wrote:
> > On 7 April 2016 7:23:46 pm AEST, Laurent Dufour
> > wrote:
> > > This series is required to handle TM state in CRIU.
> > > Is there a chance to get it upstream soon ?
> >
> > We were waiti
Comments mostly on the coding standards which you have *not* followed.
Also, please run checkpatch --strict next time you send patches
upstream.
On 12-04-16, 23:36, Akshay Adiga wrote:
> diff --git a/drivers/cpufreq/powernv-cpufreq.c
> b/drivers/cpufreq/powernv-cpufreq.c
> +#define MAX_RAMP_DOWN
Since commit ea8daa7b9784 ("kbuild: Add option to turn incompatible
pointer check into error"), assignments from an incompatible pointer
types have become a hard error, eg:
drivers/i2c/busses/i2c-cpm.c:545:91: error: passing argument 3 of
'dma_alloc_coherent' from incompatible pointer type
Fi
"Aneesh Kumar K.V" writes:
> Also note that the `~` operation is wrong.
>
> Cc: Frederic Barrat
> Cc: Andrew Donnellan
> Acked-by: Ian Munsie
> Signed-off-by: Aneesh Kumar K.V
> ---
> drivers/misc/cxl/fault.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mi
From: John Allen
Date: Tue, 12 Apr 2016 16:00:23 -0500
> On 04/12/2016 03:12 PM, Eric Dumazet wrote:
>> On Tue, 2016-04-12 at 14:38 -0500, John Allen wrote:
>>> Moves tx completion processing out of interrupt context, deferring work
>>> using a wait queue. With this work now deferred, we must acc
On Mon, 2016-11-04 at 18:57:43 UTC, Jack Miller wrote:
> Previously we just saved the FSCR, but only restored it in some
> settings, and never copied it thread to thread. This patch always
> restores the FSCR and formalizes new threads inheriting its setting so
> that later we can manipulate FSCR b
On Tue, Apr 12, 2016 at 10:51:03PM +0200, Heinrich Schuchardt wrote:
> Documentation/printk-formats.txt has
> size_t: use %zu or %zx
>
> runtime->dma_bytes is of type size_t.
>
> Signed-off-by: Heinrich Schuchardt
Acked-by: Nicolin Chen
> ---
> sound/soc/fsl/imx-pcm-fiq.c | 2 +-
> 1 file ch
Documentation/printk-formats.txt has
size_t: use %zu or %zx
runtime->dma_bytes is of type size_t.
Signed-off-by: Heinrich Schuchardt
---
sound/soc/fsl/imx-pcm-fiq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/fsl/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
inde
On 04/12/2016 03:12 PM, Eric Dumazet wrote:
> On Tue, 2016-04-12 at 14:38 -0500, John Allen wrote:
>> Moves tx completion processing out of interrupt context, deferring work
>> using a wait queue. With this work now deferred, we must account for the
>> possibility that skbs can be sent faster than
On Tue, 2016-04-12 at 14:38 -0500, John Allen wrote:
> Moves tx completion processing out of interrupt context, deferring work
> using a wait queue. With this work now deferred, we must account for the
> possibility that skbs can be sent faster than we can process completion
> requests in which cas
Moves tx completion processing out of interrupt context, deferring work
using a wait queue. With this work now deferred, we must account for the
possibility that skbs can be sent faster than we can process completion
requests in which case the tx buffer will overflow. If the tx buffer is
full, ibmv
This patch brings down global pstate at a slower rate than the local
pstate. As the frequency transition latency from pmin to pmax is
observed to be in few millisecond granurality. It takes a performance
penalty during sudden frequency rampup. Hence by holding global pstates
higher than local pstat
From: Shilpasri G Bhat
'commit 1b0289848d5d ("cpufreq: powernv: Add sysfs attributes to show throttle
stats")' used policy->driver_data as a flag for one-time creation
of throttle sysfs files. Instead of this use 'kernfs_find_and_get()'
to check if the attribute already exists. This is required a
The frequency transition latency from pmin to pmax is observed to be in few
millisecond granurality. And it usually happens to take a performance penalty
during sudden frequency rampup requests.
This patch set solves this problem by using a chip-level entity called "global
pstates". Global psta
On Sun, Apr 10, 2016 at 10:17:28PM +0800, Pan Xinhui wrote:
>
> On 2016年04月08日 15:47, Peter Zijlstra wrote:
> > On Fri, Apr 08, 2016 at 02:41:46PM +0800, Pan Xinhui wrote:
> >> From: pan xinhui
> >>
> >> Implement xchg{u8,u16}{local,relaxed}, and
> >> cmpxchg{u8,u16}{,local,acquire,relaxed}.
> >>
On Mon, Apr 11, 2016 at 11:41:29AM +1000, Suraj Jitindar Singh wrote:
> Add a binding to Documentation/devicetree/bindings/powerpc/opal
> (oppanel-opal.txt) for the operator panel which is present on IBM
> pseries machines with FSPs.
>
> Signed-off-by: Suraj Jitindar Singh
> ---
> .../devicetree
On Tue, 2016-04-12 at 17:39 +0800, kbuild test robot wrote:
> Hi Rashmica,
>
> [auto build test WARNING on v4.6-rc3]
> [also build test WARNING on next-20160412]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improving the system]
>
On Mon, 2016-04-11 at 19:12 +0530, Aneesh Kumar K.V wrote:
> Michael Ellerman writes:
> >
> > In this case it *looks* like we have a giant hole in the mm handling for
> > CAPI
> > contexts, which would let userspace create mappings of kernel memory with
> > _PAGE_USER set. I think I agree with I
Hi Alexey,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.6-rc3 next-20160412]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Alexey-Kardashevskiy/powerpc-powernv-npu
Hi Rashmica,
[auto build test WARNING on v4.6-rc3]
[also build test WARNING on next-20160412]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Rashmica-Gupta/lib-test-hexdump-Changed-to-work-on
So far, we used to treat probe point offsets as being offset from the
LEP. However, userspace applications (objdump/readelf) always show
disassembly and offsets from the function GEP. This is confusing to the
user as we will end up probing at an address different from what the
user expects when loo
ppc64le functions have a Global Entry Point (GEP) and a Local Entry
Point (LEP). While placing a probe, we always prefer the LEP since it
catches function calls through both the GEP and the LEP. In order to do
this, we fixup the function entry points during elf symbol table lookup
to point to the L
This patchset fixes three issues found with perf probe on ppc64le:
1. 'perf test kallsyms' failure on ppc64le (reported by Michael
Ellerman). This was due to the symbols being fixed up during symbol
table load. This is fixed in patch 2 by delaying symbol fixup until
later.
2. perf probe function of
NPU devices are emulated in firmware and mainly used for NPU NVLink
training; one NPU device is per a hardware link. Their DMA/TCE setup
must match the GPU which is connected via PCIe and NVLink so any changes
to the DMA/TCE setup on the GPU PCIe device need to be propagated to
the NVLink device as
IBM POWER8 NVlink systems come with Tesla K40-ish GPUs each of which
also has a couple of fast speed links (NVLink). The interface to links
is exposed as an emulated PCI bridge which is included into the same
IOMMU group as the corresponding GPU.
In the kernel, NPUs get a separate PHB of the PNV_P
The pnv_ioda_pe struct keeps an array of peers. At the moment it is only
used to link GPU and NPU for 2 purposes:
1. Access NPU quickly when configuring DMA for GPU - this was addressed
in the previos patch by removing use of it as DMA setup is not what
the kernel would constantly do.
2. Invalida
This uses the page size from iommu_table instead of hard-coded 4K.
This should cause no change in behavior.
While we are here, move bits around to prepare for further rework
which will define and use iommu_table_group_ops.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
Reviewed-b
This exports debugging helper pe_level_printk() and corresponding macroses
so they can be used in npu-dma.c.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 9 +
arch/powerpc/platforms/powernv/pci.h | 9 +
2 files changed, 10 insertions(+)
We are going to have multiple different types of PHB on the same system
with POWER8 + NVLink and PHBs will have different IOMMU ops. However
we only really care about one callback - create_table - so we can
relax the compatibility check here.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David
As in fact pnv_pci_ioda2_tce_invalidate_entire() invalidates TCEs for
the specific PE rather than the entire cache, rename it to
pnv_pci_ioda2_tce_invalidate_pe(). In later patches we will add
a proper pnv_pci_ioda2_tce_invalidate_entire().
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David G
NPU PHB TCE Kill register is exactly the same as in the rest of POWER8
so let's reuse the existing code for NPU. The only bit missing is
a helper to reset the entire TCE cache so this moves such a helper
from NPU code and renames it.
Since pnv_npu_tce_invalidate() does really invalidate the entire
IBM POWER8 NVlink systems contain usual Tesla K40-ish GPUs but also
contain a couple of really fast links between GPU and CPU. These links
are exposed to the userspace by the OPAL firmware as bridges.
In order to make these links work when GPU is passed to the guest,
these bridges need to be passed
This replaces magic constants for TCE Kill IODA2 register with macros.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
---
arch/powerpc/platforms/powernv/pci-ioda.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
On 12/04/16 14:38, Oliver O'Halloran wrote:
> Power ISAv3 extends the width of the decrementer register from 32 bits.
> The enlarged register width is implementation dependent, but reads from
> these registers are automatically sign extended to produce a 64 bit output
> when operating in large mo
On 12/04/16 14:38, Oliver O'Halloran wrote:
> POWER ISA v3 adds large decrementer (LD) mode of operation which increases
> the size of the decrementer register from 32 bits to an implementation
> defined with of up to 64 bits.
>
> This patch adds support for the LD on processors with the CPU_FTR
44 matches
Mail list logo
