Hi,
On Mon, Apr 11, 2016 at 01:57:44PM -0500, Jack Miller wrote:
> __init_FSCR:
> mfspr r3,SPRN_FSCR
> + andi. r3,r3,(~FSCR_LM)@L
> ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
> mtspr SPRN_FSCR,r3
> blr
This clears the top 48 bits as well. Shouldn't matter curren
Support for the A2 cpu was removed in commit fb5a515704d7 ("powerpc:
Remove platforms/wsp and associated pieces"), and the externs:
__setup_cpu_a2 and __restore_cpu_a2 are still around and unused, so
remove them.
Signed-off-by: Rashmica Gupta
---
arch/powerpc/kernel/cputable.c | 2 --
1 file cha
test-hexdump.c doesn't work on BE because the test data is in LE format.
So add in data for BE.
Signed-off-by: Rashmica Gupta
---
lib/test_hexdump.c | 35 +++
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/lib/test_hexdump.c b/lib/test_hexdump.c
in
Hi Oliver,
[auto build test WARNING on powerpc/next]
[also build test WARNING on v4.6-rc3 next-20160411]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Oliver-O-Halloran/powerpc-timer-large
Power ISAv3 extends the width of the decrementer register from 32 bits.
The enlarged register width is implementation dependent, but reads from
these registers are automatically sign extended to produce a 64 bit output
when operating in large mode. The HDEC always operates in large mode
while the D
POWER ISA v3 adds large decrementer (LD) mode of operation which increases
the size of the decrementer register from 32 bits to an implementation
defined with of up to 64 bits.
This patch adds support for the LD on processors with the CPU_FTR_ARCH_300
cpu feature flag set. Even for CPUs with this
Hi Alessio,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.6-rc3 next-20160411]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Alessio-Igor-Bogani/powerpc-86xx-Add
Hi Michael,
On Wed, Apr 06, 2016 at 03:00:12PM +0800, Simon Guo wrote:
> These 2 fields track whether user process has used Altivec/VSX
> registers or not. They are used by kernel to setup signal frame
> on user stack correctly regarding vector part.
>
> CRIU(Checkpoint and Restore In User space)
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> Radix and hash MMU models support different page table sizes. Make
> the #defines a variable so that existing code can work with variable
> sizes
>
> Slice related code is only used by hash, so use hash constants there
> We will replicate some of the
Implement new character device driver to allow access from user space
to the 2x16 character operator panel display present on IBM Power Systems
machines with FSPs.
This will allow status information to be presented on the display which
is visible to a user.
The driver implements a 32 character bu
Add a binding to Documentation/devicetree/bindings/powerpc/opal
(oppanel-opal.txt) for the operator panel which is present on IBM
pseries machines with FSPs.
Signed-off-by: Suraj Jitindar Singh
---
.../devicetree/bindings/powerpc/opal/oppanel-opal.txt | 14 ++
1 file changed, 14
> Re: [RFC] P9 ldmx support
These are good to go and don't need to be marked as RFC.
FWIW, we've been testing these internally and they've been solid.
> These are patches based on next to support the forthcoming ldmx
> instruction through the existing P8 EBB infrastructure. Obviously it
> doesn
On 11/04/16 15:27, Andrew Donnellan wrote:
> On 11/04/16 11:41, Suraj Jitindar Singh wrote:
>> Implement new character device driver to allow access from user space
>> to the 2x16 character operator panel display present on powernv machines.
>
> Specifically, on IBM Power Systems machines with FSPs
On Wed, Apr 06, 2016 at 01:40:36PM +1000, Alexey Kardashevskiy wrote:
> On 04/06/2016 12:41 PM, David Gibson wrote:
> >On Wed, Apr 06, 2016 at 11:45:34AM +1000, Alexey Kardashevskiy wrote:
> >>Ping?
> >>
> >>On 03/24/2016 12:42 PM, Alexey Kardashevskiy wrote:
> >>>IBM POWER8 NVlink systems come wit
Commit 39baadbf36ce ("powerpc/eeh: Remove eeh information from pci_dn")
changed the pci_dn struct by removing its EEH-related members.
As part of this clean-up, DDW mechanism was modified to read the device
configuration address from eeh_dev struct.
As a consequence, now if we disable EEH mechanis
This reverts commit 89a51df5ab1d38b257300b8ac940bbac3bb0eb9b.
The function eeh_add_device_early() is used to perform EEH initialization in
devices added later on the system, like in hotplug/DLPAR scenarios. Since the
commit 89a51df5ab1d ("powerpc/eeh: Fix crash in eeh_add_device_early() on Cell")
Adds two tests. One is a simple test to ensure that the new registers
LMRR and LMSER are properly maintained. The other actually uses the
existing EBB test infrastructure to test that LMRR and LMSER behave as
documented.
Signed-off-by: Jack Miller
---
tools/testing/selftests/powerpc/pmu/ebb/Make
This enables new registers, LMRR and LMSER, that can trigger an EBB in
userspace code when a monitored load (via the new ldmx instruction)
loads memory from a monitored space. This facility is controlled by a
new FSCR bit, LM.
This patch disables the control bit on CPU setup and enables that bit
w
Previously we just saved the FSCR, but only restored it in some
settings, and never copied it thread to thread. This patch always
restores the FSCR and formalizes new threads inheriting its setting so
that later we can manipulate FSCR bits in start_thread.
Signed-off-by: Jack Miller
---
arch/pow
All -
These are patches based on next to support the forthcoming ldmx instruction
through the existing P8 EBB infrastructure. Obviously it doesn't actually
*work* without some other patches and a P9 system, but with the context
switch change to FSCR it makes sense to get this upstream for testing
Add support for the Artesyn MVME7100 Single Board Computer.
The MVME7100 is a 6U form factor VME64 computer with:
- A two e600 cores Freescale MPC8641D CPU
- 2 GB of DDR2 onboard memory
- Four Gigabit Ethernets
- Five 16550 compatible UARTs
- One USB 2.0 port
- Two PCI/PCI
On 07/04/16 15:37, Anshuman Khandual wrote:
> Currently the function 'huge_pte_alloc' has got two versions, one for the
> BOOK3S server and the other one for the BOOK3E embedded platforms. This
> change splits only the BOOK3S server version into two parts, one for the
> ARCH_WANT_GENERAL_HUGETLB
On 2016/04/11 02:41PM, Michael Ellerman wrote:
> On Sat, 2016-04-09 at 19:12 +0530, Naveen N. Rao wrote:
> >
> > I suppose this boils down to the quirkiness of ABIv2. Though, in
> > reality, I don't think most users will notice. As I stated above, users
> > will most likely start with the disass
Michael Ellerman writes:
> On Mon, 2016-04-11 at 10:01 +0530, Aneesh Kumar K.V wrote:
>> Michael Ellerman writes:
>> > On Mon, 2016-04-11 at 14:10 +1000, Andrew Donnellan wrote:
>> > > On 29/03/16 00:42, Aneesh Kumar K.V wrote:
>> > > > I noticed this when doing radix support and have a variant
On Mon, 2016-04-11 at 11:43 +0530, Anshuman Khandual wrote:
> On 03/07/2016 03:25 PM, Anshuman Khandual wrote:
> > For partition running on PHYP, there can be a adjunct partition
> > which shares the virtual address range with the operating system.
> > Virtual address ranges which can be used by th
On Fri, 2015-06-11 at 14:45:47 UTC, =?utf-8?b?5oWV5Yas5Lqu?= wrote:
> >From 13f516acc709d88d3162e92bc891c8e39cc9fc1a Mon Sep 17 00:00:00 2001
> From: mudongliang
> Date: Fri, 6 Nov 2015 14:35:19 +0800
> Subject: [PATCH] unify the comment form and delete unused macros
>
> diff --git a/include/uapi
On 11/04/16 15:39, Anshuman Khandual wrote:
> On 04/07/2016 02:56 PM, Balbir Singh wrote:
>>
>> On 07/04/16 15:37, Anshuman Khandual wrote:
follow_huge_(pmd|pud|pgd) functions are used to walk the page table and
fetch the page struct during 'follow_page_mask' call. There are possible
>>
On Fri, 2016-19-02 at 05:38:47 UTC, Rashmica Gupta wrote:
> Currently on PPC64 changing kernel pagesize from 4K to 64K leaves
> FORCE_MAX_ZONEORDER set to 13 - which produces a compile error.
>
...
> So, update the range of FORCE_MAX_ZONEORDER from 9-64 to 8-9 for 64K pages
> and from 13-64 to 9-1
On Tue, 2016-16-02 at 12:06:05 UTC, Russell Currey wrote:
> IBM online documentation for EEH uses "extended error handling" and
> "enhanced error handling" to refer to the same thing, in different
> places. The only place mentioning it as "enhanced error handling" in the
> kernel is the MAINTAINER
On Wed, 2016-16-03 at 10:56:20 UTC, Michael Ellerman wrote:
> We have a bunch of SLB related code in the tree which is there to handle
> dynamic VSIDs - but currently it's all disabled at compile time. The
> comments say "Keep that around for when we re-implement dynamic VSIDs".
>
> But that was o
On Tue, 2016-15-03 at 10:14:12 UTC, Russell Currey wrote:
> The HMI code knows about three types of errors: CORE, NX and UNKNOWN.
> If OPAL were to add a new type, it would not be handled at all since
> there is no fallback case. Instead of explicitly checking for UNKNOWN,
> treat any checkstop ty
On Wed, 2016-02-03 at 06:12:45 UTC, Russell Currey wrote:
> If CONFIG_HIBERNATION and CONFIG_PPC_BOOK3S_64 are set, code in
> arch/powerpc/kernel/swsusp_amd64.S which uses the tlbia macro is enabled.
> tlbia in turn uses tlbie, an instruction which takes more than one
> operand in newer versions of
On Wed, 2016-02-03 at 01:36:56 UTC, Michael Ellerman wrote:
> We'd like folks working on drivers for powerpc to also Cc linuxppc-dev,
> so we can be aware of what's going on in drivers and/or review the
> changes.
>
> So add patterns to the powerpc MAINTAINERS section to catch some of the
> driver
On Wed, 2016-09-03 at 11:53:13 UTC, Frederic Barrat wrote:
> Function cxl_get_phys_dev() was removed from the kernel API by a
> previous patch, but it's actually dead code. Remove it.
>
> Signed-off-by: Frederic Barrat
> Acked-by: Ian Munsie
> Reviewed-by: Andrew Donnellan
> Acked-by: Michael N
On Mon, 2015-31-08 at 23:22:43 UTC, Vipin K Parashar wrote:
> This patch assigns numbers to OPAL_MSG macros of enum opal_msg_type
> to prevent accidental insertion of any new value in between and thus
> break OPAL API. This is also helpful while backporting mainline kernel
> changes to distros whic
On Sun, 2016-27-03 at 22:08:17 UTC, Paul Gortmaker wrote:
> The Kconfig for this driver is currently:
>
> config CPU_FREQ_CBE_PMI
> bool "CBE frequency scaling using PMI interface"
>
> ...meaning that it currently is not being built as a module by
> anyone. Lets remove the modular and unused
On Wed, 2016-10-02 at 17:12:13 UTC, Nathan Fontenot wrote:
> The associativity array index specified for a LMB in the device tree,
> /ibm,dynamic-reconfiguration-memory/ibm,dynamic-memory, needs to be updated
> prior to DLPAR adding a LMB and after DLPAR removing a LMB.
>
> Without doing this step
On Sun, 2016-27-03 at 22:08:16 UTC, Paul Gortmaker wrote:
> The Makefile/Kconfig currently controlling compilation of this code is:
>
> obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
>signal_64.o ptrace32.o \
>pac
On Wed, 2016-16-03 at 10:36:06 UTC, Michael Ellerman wrote:
> generic_memcpy() is only called from copy_32.S, so there's no reason for
> it to be global.
>
> Reported-by: Al Viro
> Signed-off-by: Michael Ellerman
Applied to powerpc next.
https://git.kernel.org/powerpc/c/b4c6afdc3a1ad73542c8e92
On Thu, 2016-31-03 at 09:19:28 UTC, Philippe Bergheaud wrote:
> The POWER8NVL chip has two CAPI ports. Configure the PSL to route
> data to the port corresponding to the CAPP unit.
>
> Signed-off-by: Philippe Bergheaud
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/aa14138a5
On Wed, 2016-10-02 at 17:10:44 UTC, Nathan Fontenot wrote:
> Re-factor dlpar_lmb_add() routine by moving the validation of the lmb
> flags and the acquireing of the DRC to a wrapper around the work to add
> the memory to the system. This is done to make handling of errors
> during the addition of t
On Sun, 2016-27-03 at 22:08:15 UTC, Paul Gortmaker wrote:
> The Kconfig currently controlling compilation of this code is:
>
> arch/powerpc/platforms/cell/Kconfig:config SPU_BASE
> arch/powerpc/platforms/cell/Kconfig:bool
>
> ...meaning that it currently is not being built as a module by anyo
On Wed, 2016-16-03 at 10:36:05 UTC, Michael Ellerman wrote:
> This has been unused since ~2004, remove it.
>
> Reported-by: Al Viro
> Signed-off-by: Michael Ellerman
Applied to powerpc next.
https://git.kernel.org/powerpc/c/b05fac783a75c6e9f3af2ce082
cheers
___
On Thu, 2016-31-03 at 09:19:27 UTC, Philippe Bergheaud wrote:
> Signed-off-by: Philippe Bergheaud
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/86c9ffcc1ed17497a5df473232
cheers
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozla
On Mon, 2016-04-11 at 10:01 +0530, Aneesh Kumar K.V wrote:
> Michael Ellerman writes:
> > On Mon, 2016-04-11 at 14:10 +1000, Andrew Donnellan wrote:
> > > On 29/03/16 00:42, Aneesh Kumar K.V wrote:
> > > > I noticed this when doing radix support and have a variant posted at
> > > >
> > > > https:
On Mon, Apr 11, 2016 at 12:00:04PM +0200, Christophe JAILLET wrote:
> Hi,
>
> while looking at potential clean-up, I ended on the following code
> which looks spurious to me.
>
> We allocate 'be16_to_cpu(scan_info->size)' bytes, but then copy
> 'scan_info->size'.
> This is not consistent.
>
Goo
this is a case for kmemdup().
target->hwinfo=kmemdup(scan_info,be16_to_cpu(scan_info->size), GFP_KERNEL);
re,
wh
Am 11.04.2016 12:00, schrieb Christophe JAILLET:
> Hi,
>
> while looking at potential clean-up, I ended on the following code which
> looks spurious to me.
>
> We allocate 'be16_
Hi,
while looking at potential clean-up, I ended on the following code which
looks spurious to me.
We allocate 'be16_to_cpu(scan_info->size)' bytes, but then copy
'scan_info->size'.
This is not consistent.
I don't know which one is the correct one.
CJ
--- drivers/net/ethernet/toshiba/ps
On 08.04.2016 18:05, Laurent Vivier wrote:
> Until now, when we connect gdb to the QEMU gdb-server, the
> single-step mode is not managed.
>
> This patch adds this, only for kvm-pr:
>
> If KVM_GUESTDBG_SINGLESTEP is set, we enable single-step trace bit in the
> MSR (MSR_SE) just before the __kvmp
On 07/04/2016 23:49, Michael Ellerman wrote:
>
>
> On 7 April 2016 7:23:46 pm AEST, Laurent Dufour
> wrote:
>> On 16/02/2016 09:59, Anshuman Khandual wrote:
>>> This patch series adds twelve new ELF core note sections which can
>>> be used with existing ptrace request PTRACE_GETREGSET-SETRE
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