On Tue, Feb 23, 2016 at 10:18:05AM +0530, Aneesh Kumar K.V wrote:
> The difference between 64K and 4K hash fault handling is confusing
> with respect to when we set _PAGE_HASHPTE in the linux pte.
> I was trying to find out whether we miss a hpte flush in any
> scenario because of this. ie, a pte u
On 23/02/16 16:30, Anshuman Khandual wrote:
On 02/23/2016 03:57 AM, Rashmica wrote:
Hi Anshuman,
Thanks for the feedback!
On 22/02/16 21:13, Anshuman Khandual wrote:
On 02/22/2016 11:32 AM, Rashmica Gupta wrote:
Useful to be able to dump the kernel page tables to check permissions
and
memo
On 02/23/2016 03:57 AM, Rashmica wrote:
> Hi Anshuman,
>
> Thanks for the feedback!
>
> On 22/02/16 21:13, Anshuman Khandual wrote:
>> On 02/22/2016 11:32 AM, Rashmica Gupta wrote:
>>> Useful to be able to dump the kernel page tables to check permissions
>>> and
>>> memory types - derived from ar
On Mon, Feb 22, 2016 at 08:05:01PM -0600, Scott Wood wrote:
> On Mon, 2016-02-22 at 16:13 +1100, Sam Bobroff wrote:
> > It can currently be difficult to diagnose a build that fails due to
> > the compiler, linker or other parts of the toolchain being unable to
> > build binaries of the type require
We will be adding a radix variant of these routines in the followup
patches. Move the hash64 variant into its own header so that we can
rename them easily later. Also split pgalloc 64k and 4k headers
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
.../include/asm/book3s/64/pgall
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/pgtable-hash64.c | 373 +++
arch/powerpc/mm/pgtable_64.c | 373 ---
2 files changed, 373 insertions(+), 373 deletions(-)
diff --git a/arch/powerpc/mm/pgtable-hash64.c b
The radix variant is going to require a flush_tlb_range. We can't then
have this as static inline because of the usage of HPAGE_PMD_SIZE. So
we are forced to make it a function in which case we can use the generic
version.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/p
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 2 +
arch/powerpc/include/asm/nohash/64/pgtable.h | 3 +
arch/powerpc/mm/Makefile | 3 +-
arch/powerpc/mm/init_64.c| 114 +
arch/powerpc/mm/mem.c
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/tlbflush-hash.h | 94 ++
arch/powerpc/include/asm/tlbflush.h| 92 +
2 files changed, 95 insertions(+), 91 deletions(-)
create mode 100644 arch/powerpc/include/asm/book3s
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/{mmu-hash32.h => book3s/32/mmu-hash.h} | 0
arch/powerpc/include/asm/{mmu-hash64.h => book3s/64/mmu-hash.h} | 0
arch/powerpc/include/asm/mmu.h | 4 ++--
arch/powerpc/kernel/idle_power7.S
This should not have any impact for hash linux implementation. But radix
would require us to flush tlb after clearing accessed bit. Also move
code that is not dependent on pte bits to generic header.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 45 +-
We move large part of fsl related code to hugetlbpage-book3e.c.
Only code movement. This also avoid #ifdef in the code.
Eventhough we allow hugetlbfs only for book3s 64 and fsl book3e, I am
still retaining the #ifdef in hugetlbpage-book3e.c. It looks like there
was an attempt to support hugetlbfs
64bit book3s now always have 4 level page table irrespective of linux
page size. Move the related code out of #ifdef
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 55 +---
1 file changed, 18 insertions(+), 37 deletions(-)
diff --git a
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgalloc.h | 6 +++---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 17 ++--
arch/powerpc/include/asm/book3s/pgalloc.h | 19 ++
.../asm/{pgalloc-32.h => nohash/32/pgalloc.h}
We now use physical address in upper page table tree levels. Even though
they are aligned to their size, for the masked bits we use the
overloaded bit positions as per PowerISA 3.0. We keep the bad bits check
as it is, and will use conditional there when adding radix. Bad bits
check also check for
This patch make a copy of pgalloc routines for book3s. The idea is to
enable a hash64 copy of these pgalloc routines which can be later
updated to have a radix conditional. Radix introduce a new page table
format with different page table size.
This mostly does:
cp pgalloc-32.h book3s/32/pgalloc.
This is needed so that we can support both hash and radix page table
using single kernel. Radix kernel uses a 4 level table.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/Kconfig | 1 +
arch/powerpc/include/asm/book3s/64/hash-4k.h | 33 +--
a
We remove real_pte_t out of STRICT_MM_TYPESCHECK.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 5 -
arch/powerpc/include/asm/pgtable-types.h | 26 +-
2 files changed, 9 insertions(+), 22 deletions(-)
diff --git a/arch/powerp
We move the page table accessors into a separate header. We will
later add a big endian variant of the table which is needed for radix.
No functionality change only code movement.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/page.h | 104 +
ar
The difference between 64K and 4K hash fault handling is confusing
with respect to when we set _PAGE_HASHPTE in the linux pte.
I was trying to find out whether we miss a hpte flush in any
scenario because of this. ie, a pte update on a linux pte, for which we
are doing a parallel hash pte insert. A
From: "Kirill A. Shutemov"
With next generation power processor, we are having a new mmu model
[1] that require us to maintain a different linux page table format.
Inorder to support both current and future ppc64 systems with a single
kernel we need to make sure kernel can select between differe
We are updating pte in those functions.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash64_4k.c | 2 +-
arch/powerpc/mm/hash64_64k.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/hash64_4k.c b/arch/powerpc/mm/hash64_4k.c
index e7c04542ba62..e3e
Hello,
This series mostly consisting of code movement. One new thing added in this
series
is to switch book3s 64 to 4 level page table. The changes are done to accomodate
the upcoming new memory model in future powerpc chips. The details of the new
MMU model can be found at
http://ibm.biz/powe
This patch adds the ability to be able to save the VSX registers to the
thread struct without giving up (disabling the facility) next time the
process returns to userspace.
This patch builds on a previous optimisation for the FPU and VEC registers
in the thread copy path to avoid a possibly pointl
Loop in assembly checking the registers with many threads.
Signed-off-by: Cyril Bur
---
tools/testing/selftests/powerpc/math/.gitignore| 2 +
tools/testing/selftests/powerpc/math/Makefile | 5 +-
tools/testing/selftests/powerpc/math/fpu_asm.S | 36 +++
tools/testing/selftes
This patch adds the ability to be able to save the FPU registers to the
thread struct without giving up (disabling the facility) next time the
process returns to userspace.
This patch optimises the thread copy path (as a result of a fork() or
clone()) so that the parent thread can return to usersp
This patch adds the ability to be able to save the VEC registers to the
thread struct without giving up (disabling the facility) next time the
process returns to userspace.
This patch builds on a previous optimisation for the FPU registers in the
thread copy path to avoid a possibly pointless relo
This prepares for the decoupling of saving {fpu,altivec,vsx} registers and
marking {fpu,altivec,vsx} as being unused by a thread.
Currently giveup_{fpu,altivec,vsx}() does both however optimisations to
task switching can be made if these two operations are decoupled.
save_all() will permit the sav
Currently the FPU, VEC and VSX facilities are lazily loaded. This is not a
problem unless a process is using these facilities.
Modern versions of GCC are very good at automatically vectorising code, new
and modernised workloads make use of floating point and vector facilities,
even the kernel make
Currently when threads get scheduled off they always giveup the FPU,
Altivec (VMX) and Vector (VSX) units if they were using them. When they are
scheduled back on a fault is then taken to enable each facility and load
registers. As a result explicitly disabling FPU/VMX/VSX has not been
necessary.
Load up the non volatile FPU and VMX regs and ensure that they are the
expected value in a signal handler
Signed-off-by: Cyril Bur
---
tools/testing/selftests/powerpc/math/.gitignore | 2 +
tools/testing/selftests/powerpc/math/Makefile | 4 +-
tools/testing/selftests/powerpc/math/fpu_s
Test that the non volatile floating point and Altivec registers get
correctly preserved across the fork() syscall.
fork() works nicely for this purpose, the registers should be the same for
both parent and child
Signed-off-by: Cyril Bur
---
tools/testing/selftests/powerpc/Makefile |
Cover-letter for V1 of the series is at
https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-November/136350.html
Cover-letter for V2 of the series is at
https://lists.ozlabs.org/pipermail/linuxppc-dev/2016-January/138054.html
Changes in V3:
Addressed review comments from Michael Neuling
- Made
On Mon, 2016-02-22 at 20:15 -0600, Scott Wood wrote:
> On Tue, 2016-02-23 at 13:04 +1100, Michael Ellerman wrote:
> > On Tue, 2016-02-16 at 15:21 -0600, Scott Wood wrote:
> > > On Thu, 2016-02-11 at 17:16 +0100, Christophe Leroy wrote:
> > > > This patch provides VIRT_CPU_ACCOUTING to PPC32 archite
This changes the Linux page tables to store physical addresses
rather than kernel virtual addresses in the upper levels of the
tree (pgd, pud and pmd) for 64-bit Book 3S machines.
This also changes the hugepd pointers used to implement hugepages
when the base page size is 4k to store physical addr
Scott Wood writes:
> On Tue, 2016-02-09 at 18:52 +0530, Aneesh Kumar K.V wrote:
>>
>> Hi Scott,
>>
>> I missed adding you on CC:, Can you take a look at this and make sure we
>> are not breaking anything on freescale.
>
> I'm having trouble getting it to apply cleanly. Do you have a git tree I
On Tue, 2016-02-23 at 13:04 +1100, Michael Ellerman wrote:
> On Tue, 2016-02-16 at 15:21 -0600, Scott Wood wrote:
>
> > On Thu, 2016-02-11 at 17:16 +0100, Christophe Leroy wrote:
>
> > > This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture.
> > > PPC32 doesn't have the PACA structure, so
On Mon, 2016-02-22 at 16:13 +1100, Sam Bobroff wrote:
> It can currently be difficult to diagnose a build that fails due to
> the compiler, linker or other parts of the toolchain being unable to
> build binaries of the type required by the kernel config. For example
> using a little endian toolchai
On Tue, 2016-02-16 at 15:21 -0600, Scott Wood wrote:
> On Thu, 2016-02-11 at 17:16 +0100, Christophe Leroy wrote:
> > This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture.
> > PPC32 doesn't have the PACA structure, so we use the task_info
> > structure to store the accounting data.
> >
>
On Tue, 2016-02-09 at 18:52 +0530, Aneesh Kumar K.V wrote:
>
> Hi Scott,
>
> I missed adding you on CC:, Can you take a look at this and make sure we
> are not breaking anything on freescale.
I'm having trouble getting it to apply cleanly. Do you have a git tree I can
test?
-Scott
> "Aneesh K
On Wed, 2016-02-17 at 17:29 +0100, Christophe Leroy wrote:
>
> Le 16/02/2016 22:21, Scott Wood a écrit :
> > On Thu, 2016-02-11 at 17:16 +0100, Christophe Leroy wrote:
> > > This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture.
> > > PPC32 doesn't have the PACA structure, so we use the tas
On Mon, Feb 22, 2016 at 10:25:51AM +0530, Aneesh Kumar K.V wrote:
> Paul Mackerras writes:
>
> > From: Paul Mackerras
> >
> > This changes the Linux page tables to store physical addresses
> > rather than kernel virtual addresses in the upper levels of the
> > tree (pgd, pud and pmd) for 64-bit
On Mon, Feb 22, 2016 at 12:36:03PM +0530, Aneesh Kumar K.V wrote:
> Paul Mackerras writes:
>
> > From: Paul Mackerras
> >
> > This changes the Linux page tables to store physical addresses
> > rather than kernel virtual addresses in the upper levels of the
> > tree (pgd, pud and pmd) for 64-bit
Hi Anshuman,
Thanks for the feedback!
On 22/02/16 21:13, Anshuman Khandual wrote:
On 02/22/2016 11:32 AM, Rashmica Gupta wrote:
Useful to be able to dump the kernel page tables to check permissions and
memory types - derived from arm64's implementation.
Add a debugfs file to check the page ta
On 2/22/2016 12:14 PM, Frederic Barrat wrote:
platoform->platform
Irreverent to the Socratic amongst us.
Hope we didn't hurt your feelings :-D
Fred
No, you did not!
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozl
On 2/22/2016 8:46 AM, Frederic Barrat wrote:
Le 21/02/2016 23:30, Manoj Kumar a écrit :
Subject: [PATCH v4 08/18] cxl: IRQ allocation for guests
Date: Tue, 16 Feb 2016 22:39:01 +0100
From: Frederic Barrat
To: imun...@au1.ibm.com, michael.neul...@au1.ibm.com,
m...@ellerman.id.au, linuxppc-dev@li
On 2/22/2016 11:57 AM, Frederic Barrat wrote:
Manoj,
Point taken. Those constants are all defined in the architecture
document (CAIA). We should probably use more macros there.
However, since those were not introduced by this patch, I'll put it in
my todo list for the future, but don't intend to
+
+/**
+ * cxl_h_validate_adapter_image - Validate the base image in the
coherent
+ *platoform facility.
platoform->platform
Irreverent to the Socratic amongst us.
Hope we didn't hurt your feelings :-D
Fred
___
Le 21/02/2016 22:44, Manoj Kumar a écrit :
Code specific to bare-metal is meant to be in native.c or pci.c
only. It's basically anything which touches the capi p1 registers,
I thought we were going to avoid using the CAPI term externally.
Please update if submitting a v4 of this patch series.
Manoj,
cxl hasn't been and is not checkpatch-clean. That being said, we tried
to not make it worse. I've let go 2 types of reports, which were already
present in the cxl code:
- lines longer than 80 characters, when it's not showing a clear sign
that code should be refactored
- assignment in
Manoj,
Point taken. Those constants are all defined in the architecture
document (CAIA). We should probably use more macros there.
However, since those were not introduced by this patch, I'll put it in
my todo list for the future, but don't intend to address it in this
patchset.
Fred
Le 2
Le 21/02/2016 23:30, Manoj Kumar a écrit :
Subject: [PATCH v4 08/18] cxl: IRQ allocation for guests
Date: Tue, 16 Feb 2016 22:39:01 +0100
From: Frederic Barrat
To: imun...@au1.ibm.com, michael.neul...@au1.ibm.com,
m...@ellerman.id.au, linuxppc-dev@lists.ozlabs.org
The PSL interrupt is not going
On 02/22/2016 11:32 AM, Rashmica Gupta wrote:
> Useful to be able to dump the kernel page tables to check permissions and
> memory types - derived from arm64's implementation.
>
> Add a debugfs file to check the page tables. To use this the PPC_PTDUMP
> config option must be selected.
>
> Tested
On Wed, 2016-17-02 at 06:06:04 UTC, Russell Currey wrote:
> Enhanced Error Handling could mean anything in the context of the entire
> kernel, so change the name to reference that it is both for PCI and
> powerpc.
>
> EEH covers a bit more than the previously listed files, so add the headers
> and
On Mon, 2016-01-02 at 06:03:25 UTC, Balbir Singh wrote:
> From: Balbir Singh
>
> I spent some time trying to use kgdb and debugged my inability to
> resume from kgdb_handle_breakpoint(). NIP is not incremented
> and that leads to a loop in the debugger.
>
> I've tested this lightly on a virtual
On Tue, 2015-15-12 at 14:24:14 UTC, Boqun Feng wrote:
> Some architectures may have their special barriers for acquire, release
> and fence semantics, so that general memory barriers(smp_mb__*_atomic())
> in the default __atomic_op_*() may be too strong, so allow architectures
> to define their own
On Mon, 2016-02-22 at 19:24 +1100, Michael Ellerman wrote:
> On Sat, 2016-20-02 at 17:58:37 UTC, Ben Hutchings wrote:
> > Soft dirty bit support was only implemented for 64-bit Book3S, and
> > 32-bit configurations currently fail to build.
> >
> > Fixes: 7207f43665b8 ("powerpc/mm: Add page soft di
Signed-off-by: Alessio Igor Bogani
---
arch/powerpc/Makefile| 10 +
arch/powerpc/configs/86xx-hw.config | 106 ++
arch/powerpc/configs/86xx-smp.config | 2 +
arch/powerpc/configs/86xx/gef_ppc9a_defconfig| 234
This patch show how defconfigs appear if the kconfig fragment approach is
used.
Signed-off-by: Alessio Igor Bogani
---
v1 -> v2
Split changes in two patches as suggested by Scott Wood
arch/powerpc/configs/86xx/gef_ppc9a_defconfig| 208 +++---
arch/powerpc/configs/86xx/gef_sb
On Sat, 2016-20-02 at 17:58:37 UTC, Ben Hutchings wrote:
> Soft dirty bit support was only implemented for 64-bit Book3S, and
> 32-bit configurations currently fail to build.
>
> Fixes: 7207f43665b8 ("powerpc/mm: Add page soft dirty tracking")
> References:
> https://buildd.debian.org/status/fetc
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