Paul Mackerras writes:
> From: Paul Mackerras
>
> This changes the Linux page tables to store physical addresses
> rather than kernel virtual addresses in the upper levels of the
> tree (pgd, pud and pmd) for 64-bit Book 3S machines.
>
> This frees up some high order bits, and will be needed wit
Useful to be able to dump the kernel page tables to check permissions and
memory types - derived from arm64's implementation.
Add a debugfs file to check the page tables. To use this the PPC_PTDUMP
config option must be selected.
Tested on 64BE and 64LE with both 4K and 64K page sizes.
---
arch/
It can currently be difficult to diagnose a build that fails due to
the compiler, linker or other parts of the toolchain being unable to
build binaries of the type required by the kernel config. For example
using a little endian toolchain to build a big endian kernel may
produce:
as: unrecognized
Paul Mackerras writes:
> From: Paul Mackerras
>
> This changes the Linux page tables to store physical addresses
> rather than kernel virtual addresses in the upper levels of the
> tree (pgd, pud and pmd) for 64-bit Book 3S machines.
>
> This frees up some high order bits, and will be needed wit
From: Paul Mackerras
Now that other PTE fields have been moved out of the way, we can
expand the RPN field of the PTE on 64-bit Book 3S systems and align
it with the RPN field in the radix PTE format used by PowerISA v3.0
CPUs in radix mode. For 64k page size, this means we need to move
the _PAG
From: Paul Mackerras
This moves the _PAGE_SPECIAL and _PAGE_SOFT_DIRTY bits in the Linux
PTE on 64-bit Book 3S systems to bit positions which are designated
for software use in the radix PTE format used by PowerISA v3.0 CPUs
in radix mode.
Signed-off-by: Paul Mackerras
---
arch/powerpc/include
From: Paul Mackerras
This moves the _PAGE_EXEC, _PAGE_RW and _PAGE_USER bits around in
the Linux PTE on 64-bit Book 3S systems to correspond with the bit
positions used in radix mode by PowerISA v3.0 CPUs. This also adds
a _PAGE_READ bit corresponding to the read permission bit in the
radix PTE.
From: Paul Mackerras
This moves the _PAGE_HASHPTE, _PAGE_F_GIX and _PAGE_F_SECOND fields in
the Linux PTE on 64-bit Book 3S systems to the most significant byte.
Of the 5 bits, one is a software-use bit and the other four are
reserved bit positions in the PowerISA v3.0 radix PTE format.
Using the
From: Paul Mackerras
This changes _PAGE_PTE for 64-bit Book 3S processors from 0x1 to
0x4000___, because that bit is used as the L (leaf)
bit by PowerISA v3.0 CPUs in radix mode. The "leaf" bit indicates
that the PTE points to a page directly rather than another radix
level, which is
From: Paul Mackerras
This changes _PAGE_PRESENT for 64-bit Book 3S processors from 0x2 to
0x8000___, because that is where PowerISA v3.0 CPUs in
radix mode will expect to find it.
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 10 +-
arch/
From: Paul Mackerras
This changes the Linux page tables to store physical addresses
rather than kernel virtual addresses in the upper levels of the
tree (pgd, pud and pmd) for 64-bit Book 3S machines.
This frees up some high order bits, and will be needed with
PowerISA v3.0 machines which read t
From: Paul Mackerras
This frees up bits 57-63 in the Linux PTE on 64-bit Book 3S machines.
In the 4k page case, this is done just by reducing the size of the
RPN field to 39 bits, giving 51-bit real addresses. In the 64k page
case, we had 10 unused bits in the middle of the PTE, so this moves
th
This patch series modifies the Linux PTE format used on 64-bit Book3S
processors (i.e. POWER server processors) to make the bits line up
with the PTE format used in the radix trees defined in PowerISA v3.0.
This will reduce the amount of further change required to make a
kernel that can run with ei
From: Paul Mackerras
No code changes.
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/book3s/64/hash.h | 13 ++---
arch/powerpc/mm/hash64_64k.c | 3 +--
arch/powerpc/mm/hash_utils_64.c | 10 +-
3 files changed, 12 insertions(+), 14 deletions(-
Christophe, Fred:
Is getting the code checkpatch clean not a requirement for
this component?
total: 458 errors, 995 warnings, 1602 lines checked
NOTE: Whitespace errors detected.
You may wish to use scripts/cleanpatch or scripts/cleanfile
I am stopping my review at this point.
Will pick
Christophe, Fred: Perhaps none of these comments below are specific
to your patch, but clarification would help the next reviewer.
--
Manoj Kumar
Subject: [PATCH v4 11/18] cxl: Separate bare-metal fields in adapter and
-WARN_ON(afu->spa_size > 0x10); /* Max size supported by the
har
On Sat, 2016-02-20 at 20:10 +0530, Aneesh Kumar K.V wrote:
> Paul Mackerras writes:
>
> > This patch series modifies the Linux PTE format used on 64-bit Book3S
> > processors (i.e. POWER server processors) to make the bits line up
> > with the PTE format used in the radix trees defined in PowerIS
On Mon, 2016-02-22 at 09:36 +1100, Paul Mackerras wrote:
> On Sun, Feb 21, 2016 at 01:00:54PM +0530, Aneesh Kumar K.V wrote:
> > Paul Mackerras writes:
> >
> > Also can you use constants like
> > #define _PAGE_USER PPC_BIT(60)
>
> I'd really rather not - that is harder for the casual reader to par
Fred: See comments below.
The most egregious checkpatch violations so far in this series,
for going beyond 80 columns.
total: 65 warnings, 924 lines checked
On 2/21/2016 3:31 PM, Uma Krishnan wrote:
From: Christophe Lombard
The hypervisor calls provide an interface with a coherent plaform
Reviewed-by: Manoj Kumar
---
Manoj Kumar
Subject: [PATCH v4 09/18] cxl: New possible return value from hcall
Date: Tue, 16 Feb 2016 22:39:02 +0100
From: Frederic Barrat
To: imun...@au1.ibm.com, michael.neul...@au1.ibm.com,
m...@ellerman.id.au, linuxppc-dev@lists.ozlabs.org
From: Christophe
On Sun, Feb 21, 2016 at 01:00:54PM +0530, Aneesh Kumar K.V wrote:
> Paul Mackerras writes:
>
> > This moves the _PAGE_EXEC, _PAGE_RW and _PAGE_USER bits around in
> > the Linux PTE on 64-bit Book 3S systems to correspond with the bit
> > positions used in radix mode by PowerISA v3.0 CPUs. This a
On Sat, Feb 20, 2016 at 10:05:58PM +0530, Aneesh Kumar K.V wrote:
> Paul Mackerras writes:
>
> > This changes the Linux page tables to store physical addresses
> > rather than kernel virtual addresses in the upper levels of the
> > tree (pgd, pud and pmd) for all 64-bit machines.
> >
> > This fre
On Sun, Feb 21, 2016 at 01:11:17PM +0530, Aneesh Kumar K.V wrote:
> "Aneesh Kumar K.V" writes:
>
> > Paul Mackerras writes:
> >
> >> This patch series modifies the Linux PTE format used on 64-bit Book3S
> >> processors (i.e. POWER server processors) to make the bits line up
> >> with the PTE for
On Sat, Feb 20, 2016 at 10:11:14PM +0530, Aneesh Kumar K.V wrote:
> Paul Mackerras writes:
>
> > This changes _PAGE_PRESENT for 64-bit Book 3S processors from 0x2 to
> > 0x8000___, because that is where PowerISA v3.0 CPUs in
> > radix mode will expect to find it.
>
> All the changes
On Sat, Feb 20, 2016 at 09:46:19PM +0530, Aneesh Kumar K.V wrote:
> Paul Mackerras writes:
>
> > This frees up bits 57-63 in the Linux PTE on 64-bit Book 3S machines.
> > In the 4k page case, this is done just by reducing the size of the
> > RPN field to 39 bits, giving 51-bit real addresses. In
Fred: See comment below.
---
Manoj Kumar
Subject: [PATCH v4 08/18] cxl: IRQ allocation for guests
Date: Tue, 16 Feb 2016 22:39:01 +0100
From: Frederic Barrat
To: imun...@au1.ibm.com, michael.neul...@au1.ibm.com,
m...@ellerman.id.au, linuxppc-dev@lists.ozlabs.org
The PSL interrupt is not going
Reviewed-by: Manoj Kumar
---
Manoj Kumar
Subject: [PATCH v4 07/18] cxl: Update cxl_irq() prototype
Date: Tue, 16 Feb 2016 22:39:00 +0100
From: Frederic Barrat
To: imun...@au1.ibm.com, michael.neul...@au1.ibm.com,
m...@ellerman.id.au, linuxppc-dev@lists.ozlabs.org
The context parameter when
Reviewed-by: Manoj Kumar
---
Manoj Kumar
Subject: [PATCH v4 06/18] cxl: Isolate a few bare-metal-specific calls
Date: Tue, 16 Feb 2016 22:38:59 +0100
From: Frederic Barrat
To: imun...@au1.ibm.com, michael.neul...@au1.ibm.com,
m...@ellerman.id.au, linuxppc-dev@lists.ozlabs.org
A few function
Reviewed-by: Manoj Kumar
---
Manoj Kumar
Subject: [PATCH v4 05/18] cxl: Rename some bare-metal specific functions
Date: Tue, 16 Feb 2016 22:38:58 +0100
From: Frederic Barrat
To: imun...@au1.ibm.com, michael.neul...@au1.ibm.com,
m...@ellerman.id.au, linuxppc-dev@lists.ozlabs.org
Rename a fe
Reviewed-by: Manoj Kumar
---
Manoj Kumar
Subject: [PATCH v4 04/18] cxl: Introduce implementation-specific API
Date: Tue, 16 Feb 2016 22:38:57 +0100
From: Frederic Barrat
To: imun...@au1.ibm.com, michael.neul...@au1.ibm.com,
m...@ellerman.id.au, linuxppc-dev@lists.ozlabs.org
The backend API
Reviewed-by: Manoj Kumar
---
Manoj Kumar
Subject: [PATCH v4 03/18] cxl: Define process problem state area at
attach time only
Date: Tue, 16 Feb 2016 22:38:56 +0100
From: Frederic Barrat
To: imun...@au1.ibm.com, michael.neul...@au1.ibm.com,
m...@ellerman.id.au, linuxppc-dev@lists.ozlabs.org
Reviewed-by: Manoj Kumar
---
Manoj Kumar
--
Subject: [PATCH v4 02/18] cxl: Move bare-metal specific code to
specialized files
Date: Tue, 16 Feb 2016 22:38:55 +0100
From: Frederic Barrat
To: imun...@au1.ibm.com, michael.neul...@au1.ibm.com,
m...@ellerman.id.au, linuxppc-dev@lists.ozlabs.org
Would have been nice to have the code and the commit messages
consistent in the terminology.
Commit comments: bare-metal and guest
Code: powernv and phyp
Reviewed-by: Manoj Kumar
---
Manoj Kumar
Forwarded Message
Subject: [PATCH v4 01/18] cxl: Move common code away from
ba
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