On 11/28/2015 10:39 PM, Aneesh Kumar K.V wrote:
> This is the same bug we fixed as part of
> 09567e7fd44291bfc08accfdd67ad8f467842332
> ("powerpc/mm: Check paca psize is up to date for huge mappings"). Please
> check that for details. The difference here is that faults were
> happening on a 4K pag
On 01/12/15 16:08, Rashmica Gupta wrote:
This is reliant on the following patch series:
- selftests/powerpc by Michael Ellerman
- selftests/powerpc by Michael Neuling
- powerpc/tm by Michael Neuling
Could you provide the full titles of the patch series? (Links to
patchwork.ozlabs.org are good
Enable TWR_P102x option by default in mpc85xx_basic_defconfig to support
p1025twr board.
Signed-off-by: Pengbo Li
---
arch/powerpc/configs/mpc85xx_basic_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/configs/mpc85xx_basic_defconfig
b/arch/powerpc/configs/mpc85xx_basi
The resched-dscr test does not currently check for TM, so add in check.
Signed-off-by: Rashmica Gupta
---
tools/testing/selftests/powerpc/tm/tm-resched-dscr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c
b/tools/testing/selftests/pow
This test does a fork syscall inside a transaction. Basic sniff test to see
if we can enter the kernel during a transaction.
Signed-off-by: Rashmica Gupta
---
tools/testing/selftests/powerpc/tm/.gitignore | 1 +
tools/testing/selftests/powerpc/tm/Makefile | 2 +-
tools/testing/selftests/powe
Currently tbegin, tend etc are written as opcodes or asm instructions. So
standardise these to asm instructions.
Signed-off-by: Rashmica Gupta
---
tools/testing/selftests/powerpc/tm/tm-resched-dscr.c | 16 ++--
tools/testing/selftests/powerpc/tm/tm-signal-stack.c | 4 ++--
2 files c
This is reliant on the following patch series:
- selftests/powerpc by Michael Ellerman
- selftests/powerpc by Michael Neuling
- powerpc/tm by Michael Neuling
Rashmica Gupta (3):
selftests/powerpc: Standardise TM calls
selftests/powerpc: Add test for forking inside transaction
selftests/po
On Fri, 2015-11-27 at 15:45 +1100, Stewart Smith wrote:
> Long ago, only in the lab, there was OPALv1 and OPALv2. Now there is
> just OPALv3, with nobody ever expecting anything on pre-OPALv3 to
> be cared about or supported by mainline kernels.
>
> So, let's remove FW_FEATURE_OPAL and instead us
All users of QPACE have upgraded to QPACE2 so remove the Cell QPACE code.
Signed-off-by: Rashmica Gupta
---
Also removed the reference to QPACE in the Documentation.
Documentation/devicetree/bindings/serial/8250.txt | 1 -
arch/powerpc/boot/Makefile| 2 -
arch/powerp
On Mon, 2015-11-30 at 17:31 +0530, Vipin K Parashar wrote:
> On Thursday 26 November 2015 02:50 PM, Vasant Hegde wrote:
> > On 11/18/2015 02:12 PM, Vipin K Parashar wrote:
> > > Kernel prints respective warnings about various EPOW events for
> > > user information/action after parsing EPOW interrup
Remove the related functions and #defines
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/nohash/64/pgtable.h | 33
1 file changed, 33 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h
b/arch/powerpc/include/asm/nohash/64/pgtable.h
Instead of open coding it in multiple code paths, export the helper
and add more documentation. Also make sure we don't make assumption
regarding pte bit position
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h | 1 +
arch/powerpc/mm/hash64_4k
They don't need to track 4k subpage slot details and hence don't need
second half of pgtable_t.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/nohash/64/pgtable-64k.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/64/pgtabl
W.r.t hugetlb, we support two format for pmd. With book3s_64 and
64K linux page size, we can have pte at the pmd level. Hence we
don't need to support hugepd there. For everything else hugepd
is supported and pmd_huge is (0).
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc
pte and pmd table size are dependent on config items. Don't
hard code the same. This make sure we use the right value
when masking pmd entries and also while checking pmd_bad
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h| 30 ++--
arch/
The slot information of base page size hash pte is stored in the
pgtable_t w.r.t transparent hugepage. We need to make sure we don't
index beyond pgtable_t size.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hugepage-hash64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
We support THP only with book3s_64 and 64K page size. Move
THP details to hash64-64k.h to clarify the same.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 126 +
arch/powerpc/include/asm/book3s/64/hash.h | 223 +--
This is similar to 64K insert. May be we want to consolidate
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/Makefile| 6 +-
arch/powerpc/mm/hash64_4k.c | 139 +
arch/powerpc/mm/hash_low_64.S | 331
This will bulk read 4 hash pte slot entries and should reduce the loop
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/plpar_wrappers.h | 17 ++
arch/powerpc/platforms/pseries/lpar.c | 54 +++
2 files changed, 44 insertions(+), 27 deletions(-)
For a pte entry we will have _PAGE_PTE set. Our pte page
address have a minimum alignment requirement of HUGEPD_SHIFT_MASK + 1.
We use the lower 7 bits to indicate hugepd. ie.
For pmd and pgd we can find:
1) _PAGE_PTE set pte -> indicate PTE
2) bits [2..6] non zero -> indicate hugepd.
They also
No real change, only style changes
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h
b/arch/powerpc/includ
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/Makefile| 3 +
arch/powerpc/mm/hash64_64k.c| 202 +
arch/powerpc/mm/hash_low_64.S | 380
arch/powerpc/mm/hash_utils_64.c | 4 +-
4 files changed
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/nohash/32/pte-40x.h | 6 +++---
arch/powerpc/include/asm/nohash/32/pte-44x.h | 6 +++---
arch/powerpc/include/asm/nohash/32/pte-8xx.h | 6 +++---
arch/powerpc/include/asm/nohash/32/pte-fsl-booke.h
Use the #define instead of open-coding the same
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +-
arch/powerpc/include/asm/book3s/64/pgtable.h | 2 +-
arch/powerpc/include/asm/nohash/64/pgtable.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
Only difference here is, we apply the WIMG mapping early, so rflags
passed to updatepp will also be changed.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash64_4k.c | 5 -
arch/powerpc/mm/hash64_64k.c | 10 --
arch/powerpc/mm/hash_utils
We should not expect pte bit position in asm code. Simply
by moving part of that to C
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/exceptions-64s.S | 18 --
arch/powerpc/mm/hash_utils_64.c | 29 +
2 files changed,
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 4 +++-
arch/powerpc/mm/hash64_64k.c | 1 -
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h
b/arch/powerpc/include/asm/book3s/64/hash-
Convert from asm to C
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 3 +-
arch/powerpc/mm/hash64_64k.c | 130
arch/powerpc/mm/hash_low_64.S | 290 +-
arch/powerpc/m
This free up 11 bits in pte_t. In the later patch we also change
the pte_t format so that we can start supporting migration pte
at pmd level. We now track 4k subpage valid bit as below
If we have _PAGE_COMBO set, we override the _PAGE_F_GIX_SHIFT
and _PAGE_F_SECOND. Together we have 4 bits, each o
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
.../include/asm/{pgtable-ppc64-4k.h => nohash/64/pgtable-4k.h} | 0
.../asm/{pgtable-ppc64-64k.h => nohash/64/pgtable-64k.h} | 0
arch/powerpc/include/asm/nohash/64/pgtable.h | 10 +-
3 files changed, 5 in
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/nohash/32/pgtable.h | 16
arch/powerpc/include/asm/{ => nohash/32}/pte-40x.h | 0
arch/powerpc/include/asm/{ => nohash/32}/pte-44x.h | 0
arch/powerpc/include/asm/{ => noh
This enables us to keep hash64 related bits together, and makes it easy
to follow.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 448 ++-
arch/powerpc/include/asm/book3s/64/pgtable.h | 445 +---
Move the booke related headers below booke/32 or booke/64
We are splitting this change into multiple patch to make the rebasing
easier. The following patches can be folded into this if needed.
They are kept separate for easier review.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
ar
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/{pgtable-ppc32.h => nohash/32/pgtable.h} | 0
arch/powerpc/include/asm/{pgtable-ppc64.h => nohash/64/pgtable.h} | 2 +-
arch/powerpc/include/asm/nohash/pgtable.h | 8
3 files change
functions which operate on pte bits are moved to hash*.h and other
generic functions are moved to pgtable.h
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 183
arch/powerpc/include/asm/book3s/64/hash.h| 151 ++
We also convert few #define to static inline in this patch for better
type checking
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/pgtable.h | 118 +-
arch/powerpc/include/asm/page.h | 10 ++-
arch/powerpc/include/
Keep it seperate to make rebasing easier
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 6 +++---
arch/powerpc/include/asm/book3s/64/pgtable.h | 6 +++---
arch/powerpc/include/asm/pgtable-ppc32.h | 2 --
arch/powerpc/include/asm/pgtab
We convert them static inline function here as we did with pte_val in
the previous patch
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 6 -
arch/powerpc/include/asm/book3s/64/hash-4k.h | 6 -
arch/powerpc/include/asm/book3s/64/
This further make a copy of pte defines to book3s/64/hash*.h. This
remove the dependency on pgtable-ppc64-4k.h and pgtable-ppc64-64k.h
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-4k.h | 86 ++-
arch/powerpc/include/as
We are going to drop pte_common.h in the later patch. The idea is to
enable hash code not require to define all PTE bits. Having PTE bits
defined in pte_common.h made the code unnecessarily complex.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/pgtable
In this patch we do:
cp pgtable-ppc32.h book3s/32/pgtable.h
cp pgtable-ppc64.h book3s/64/pgtable.h
This enable us to do further changes to hash specific config.
We will change the page table format for 64bit hash in later patches.
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/p
We copy only needed PTE bits define from pte-common.h to respective
hash related header. This should greatly simply later patches in which
we are going to change the pte format for hash config
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-4k.h
We also move __ASSEMBLY__ towards the end of header. This avoid
having #ifndef __ASSEMBLY___ all over the header
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 93 +++-
arch/powerpc/include/asm/book3s/64/pgtable.h
Splitting this so that rename can track changes to file. Before merging
we will fold this
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/hash.h | 6 +++---
.../include/asm/{pte-hash64-4k.h => book3s/64/hash-4k.h} | 0
...
Hi All,
This patch series attempt to update book3s 64 linux page table format to
make it more flexible. Our current pte format is very restrictive and we
overload multiple pte bits. This is due to the non-availability of free bits
in pte_t. We use pte_t to track the validity of 4K subpages. This p
Acked-by: Scott Wood
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/{pte-hash32.h => book3s/32/hash.h} | 0
arch/powerpc/include/asm/{pte-hash64.h => book3s/64/hash.h} | 0
arch/powerpc/include/asm/pgtable-ppc32.h| 2 +-
arch/powerpc/include/asm/pgtable-ppc64.h
On Thu, 2015-11-26 at 13:39 +0100, Thomas Huth wrote:
> On 26/11/15 13:09, Michael Ellerman wrote:
> > On Thu, 2015-11-26 at 11:47 +0100, Thomas Huth wrote:
> > > On 26/11/15 01:59, Rashmica Gupta wrote:
> > > > All users of QPACE have upgraded to QPACE2 so remove the Cell QPACE
> > > > code.
> >
From: Andi Kleen
Add support for the "frontend" extra MSR on Skylake in the JSON
conversion.
Signed-off-by: Andi Kleen
---
tools/perf/pmu-events/jevents.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 5a28baf..042bc3
From: Andi Kleen
The JSON event lists use a different encoding for fixed counters
than perf for instructions and cycles (ref-cycles is ok)
This lead to some common events like inst_retired.any
or cpu_clk_unhalted.thread not counting, when specified with their
JSON name.
Special case these event
From: Andi Kleen
Make alias matching the events parser case-insensitive. This is useful
with the JSON events. perf uses lower case events, but the CPU manuals
generally use upper case event names. The JSON files use lower
case by default too. But if we search case insensitively then
users can cut
Signed-off-by: Sukadev Bhattiprolu
Acked-by: Jiri Olsa
---
tools/perf/pmu-events/README | 122 +++
1 file changed, 122 insertions(+)
create mode 100644 tools/perf/pmu-events/README
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
From: Andi Kleen
To work with existing mapfiles, assume that the first line in
'mapfile.csv' is a header line and skip over it.
Signed-off-by: Andi Kleen
Signed-off-by: Sukadev Bhattiprolu
Acked-by: Jiri Olsa
---
Changelog[v2]
All architectures may not use the "Family" to identify. S
From: Andi Kleen
Add support to group the output of perf list by the Topic field
in the JSON file.
Example output:
% perf list
...
Cache:
l1d.replacement
[L1D data line replacements]
l1d_pend_miss.pending
[L1D miss oustandings duration in cycles]
l1d_pend_miss.pending_cycles
Allow assigning categories "Topics" field to the PMU events i.e.
process the topic field from the JSON file and add a corresponding
topic field to the generated C events tables.
Signed-off-by: Andi Kleen
Signed-off-by: Sukadev Bhattiprolu
Acked-by: Jiri Olsa
---
Changelog[v14]
[Jiri O
Previously we were dropping the useful longer descriptions that some
events have in the event list completely. This patch makes them appear with
perf list.
Old perf list:
baclears:
baclears.all
[Counts the number of baclears]
vs new:
perf list -v:
...
baclears:
baclears.all
[T
Implement support in jevents to parse long descriptions for events
that may have them in the JSON files. A follow on patch will make this
long description available to user through the 'perf list' command.
Signed-off-by: Andi Kleen
Signed-off-by: Sukadev Bhattiprolu
Acked-by: Jiri Olsa
---
Cha
Previously we were dropping the useful longer descriptions that some
events have in the event list completely. Now that jevents provides
support for longer descriptions (see previous patch), add support for
parsing the long descriptions
Signed-off-by: Andi Kleen
Signed-off-by: Sukadev Bhattiprolu
From: Andi Kleen
Add a PERF_CPUID variable to override the CPUID of the current CPU (within
the current architecture). This is useful for testing, so that all event
lists can be tested on a single system.
Signed-off-by: Andi Kleen
Signed-off-by: Sukadev Bhattiprolu
Acked-by: Jiri Olsa
---
v2
From: Andi Kleen
Add a --no-desc flag to perf list to not print the event descriptions
that were earlier added for JSON events. This may be useful to
get a less crowded listing.
It's still default to print descriptions as that is the more useful
default for most users.
Signed-off-by: Andi Kleen
From: Andi Kleen
Automatically adapt the now wider and word wrapped perf list
output to wider terminals. This requires querying the terminal
before the auto pager takes over, and exporting this
information from the pager subsystem.
Signed-off-by: Andi Kleen
Signed-off-by: Sukadev Bhattiprolu
A
From: Andi Kleen
Add support to print alias descriptions in perf list, which
are taken from the generated event files.
The sorting code is changed to put the events with descriptions
at the end. The descriptions are printed as possibly multiple word
wrapped lines.
Example output:
% perf list
.
From: Andi Kleen
Implement the code to match CPU types to mapfile types for x86
based on CPUID. This extends an existing similar function,
but changes it to use the x86 mapfile cpu description.
This allows to resolve event lists generated by jevents.
Signed-off-by: Andi Kleen
Signed-off-by: Suk
At run time (when 'perf' is starting up), locate the specific table
of PMU events that corresponds to the current CPU. Using that table,
create aliases for the each of the PMU events in the CPU. The use
these aliases to parse the user specified perf event.
In short this would allow the user to spe
Implement code that returns the generic CPU ID string for Powerpc.
This will be used to identify the specific table of PMU events to
parse/compare user specified events against.
Signed-off-by: Sukadev Bhattiprolu
Acked-by: Jiri Olsa
---
Changelog[v14]
- [Jiri Olsa] Move this independent
From: Andi Kleen
This is a modified version of an earlier patch by Andi Kleen.
We expect architectures to describe the performance monitoring events
for each CPU in a corresponding JSON file, which look like:
[
{
"EventCode": "0x00",
"UMask": "0x01",
"Eve
From: Andi Kleen
I need a JSON parser. This adds the simplest JSON
parser I could find -- Serge Zaitsev's jsmn `jasmine' --
to the perf library. I merely converted it to (mostly)
Linux style and added support for non 0 terminated input.
The parser is quite straight forward and does not
copy any
CPUs support a large number of performance monitoring events (PMU events)
and often these events are very specific to an architecture/model of the
CPU. To use most of these PMU events with perf, we currently have to identify
them by their raw codes:
perf stat -e r100f2 sleep 1
This patchs
On Wed, Oct 21, 2015 at 12:17:35PM -0200, Guilherme G. Piccoli wrote:
> Commit 1851617cd2da ("PCI/MSI: Disable MSI at enumeration even if kernel
> doesn't support MSI") changed the location of the code that initializes
> dev->msi_cap/msix_cap and disables MSI/MSI-X interrupts at PCI probe
> time in
On Mon, Nov 30, 2015 at 06:08:23PM +0100, Christian Zigotzky wrote:
> Hi All,
>
> I have tested the PA Semi Ethernet with the kernels 4.2.3 and 4.3.0
> today. With the kernel 4.2.3 it works but with the kernel 4.3.0
> final it doesn't work.
>
> After that I tested some git kernels and release can
Hi All,
I have tested the PA Semi Ethernet with the kernels 4.2.3 and 4.3.0
today. With the kernel 4.2.3 it works but with the kernel 4.3.0 final it
doesn't work.
After that I tested some git kernels and release candidates of 4.3.
Kernel 4.3 git from Tue Sep 01, 2015 -> PA Semi Ethernet work
From: Igal Liberman
This patch adds the Ethernet MAC driver supporting the three
different types of MACs: dTSEC, tGEC and mEMAC.
Signed-off-by: Igal Liberman
---
drivers/net/ethernet/freescale/fman/Makefile |3 +-
drivers/net/ethernet/freescale/fman/mac.c| 988
From: Igal Liberman
Add the Data Path Acceleration Architecture Frame Manger Port Driver.
The FMan driver uses a module called "Port" to represent the physical
TX and RX ports.
Each FMan version has different number of physical ports.
This patch adds The FMan Port configuration, initialization an
From: Igal Liberman
The Storage Profiles contain parameters that are used
by the FMan for frame reception and transmission.
Signed-off-by: Igal Liberman
---
drivers/net/ethernet/freescale/fman/Makefile |2 +-
drivers/net/ethernet/freescale/fman/fman_sp.c | 167 +
From: Igal Liberman
Add the Data Path Acceleration Architecture Frame Manger Driver.
The FMan embeds a series of hardware blocks that implement a group
of Ethernet interfaces. This patch adds The FMan configuration,
initialization and runtime control routines.
The FMan driver supports several ha
From: Igal Liberman
Add Frame Manager Multi-User RAM support.
This internal FMan memory block is used by the
FMan hardware modules, the management being made
through the generic allocator.
The FMan Internal memory, for example, is used for
allocating transmit and receive FIFOs.
Signed-off-by: I
From: Igal Liberman
The Freescale Data Path Acceleration Architecture (DPAA) is a set
of hardware components on specific QorIQ multicore processors.
This architecture provides the infrastructure to support
simplified sharing of networking interfaces and accelerators
by multiple CPU cores and the
User space checkpoint and restart tool (CRIU) needs the page's change
to be soft tracked. This allows to do a pre checkpoint and then dump
only touched pages.
This is done by using a newly assigned PTE bit (_PAGE_SOFT_DIRTY) when
the page is backed in memory, and a new _PAGE_SWP_SOFT_DIRTY bit whe
On Fri 2015-11-27 17:26:16, Max Filippov wrote:
Hi Max,
> > Another exception is Xtensa architecture that uses just a
> > fake NMI.
>
> It's called fake because it's actually maskable, but sometimes
> it is safe to use it as NMI (when there are no other IRQs at the
> same priority level and that
On Thursday 26 November 2015 02:50 PM, Vasant Hegde wrote:
On 11/18/2015 02:12 PM, Vipin K Parashar wrote:
Kernel prints respective warnings about various EPOW events for
user information/action after parsing EPOW interrupts. At times
below EPOW reset event warning is seen to be flooding kerne
Hi Denis,
Thank you for your answer. Sorry because of my description.
Yes, the driver probe function finds the device.
With kernel 4.4-rc3:
dmesg | grep -i eth0
[ 2.297473] eth0: PA Semi GMAC: intf 5, hw addr 02:00:e0:0a:30:00
dhclient eth0
RTNETLINK answers: Cannot allocate memory
With ke
On 11/29/15, Christian Zigotzky wrote:
> Hi All,
>
> Does the ethernet interface on your Electra, Chitra, Nemo, and Athena
> board work with the release candidates of the kernel 4.4? Unfortunately
> the P.A. Semi ethernet doesn't work on our Nemo boards with the release
> candidates of the kernel
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