On Sun, 2015-09-08 at 00:51:35 UTC, Paul Gortmaker wrote:
> The Kconfig currently controlling compilation of this code is:
>
> drivers/tty/hvc/Kconfig:config HVC_DRIVER
> drivers/tty/hvc/Kconfig:bool
>
> ...meaning that it currently is not being built as a module by anyone.
>
> Lets remo
On 08/06/2015 02:11 PM, Gavin Shan wrote:
The patch enables M64 window on P7IOC, which has been enabled on
PHB3. Different from PHB3 where 16 M64 BARs are supported and each
of them can be owned by one particular PE# exclusively or divided
evenly to 256 segments, each P7IOC PHB has 16 M64 BARs an
On 08/06/2015 02:11 PM, Gavin Shan wrote:
The series of patches intend to support PCI slot for PowerPC PowerNV platform,
which is running on top of skiboot firmware. The patchset requires corresponding
changes from skiboot firmware, which is sent to skib...@lists.ozlabs.org
for review. The PCI sl
Michael Ellerman writes:
> The relation between CONFIG_PPC_HAS_HASH_64K and CONFIG_PPC_64K_PAGES is
> painfully complicated.
>
> But if we rearrange it enough we can see that PPC_HAS_HASH_64K
> essentially depends on PPC_STD_MMU_64 && PPC_64K_PAGES.
>
> We can then notice that PPC_HAS_HASH_64K is
Michael Ellerman writes:
> For config options with only a single value, guarding the single value
> with 'if' is the same as adding a 'depends' statement. And it's more
> standard to just use 'depends'.
>
> And if the option has both an 'if' guard and a 'depends' we can collapse
> them into a sin
Michael Ellerman writes:
> Now that support for 64k pages with a 4K kernel is removed, this code is
> unreachable.
>
> CONFIG_PPC_HAS_HASH_64K can only be true when CONFIG_PPC_64K_PAGES is
> also true.
>
> But when CONFIG_PPC_64K_PAGES is true we include pte-hash64.h which
> includes pte-hash64-6
Michael Ellerman writes:
> The powerpc kernel can be built to have either a 4K PAGE_SIZE or a 64K
> PAGE_SIZE.
>
> However when built with a 4K PAGE_SIZE there is an additional config
> option which can be enabled, PPC_HAS_HASH_64K, which means the kernel
> also knows how to hash a 64K page even
Hello Scott,
T1040D4RDB, T1042D4RDB are completely new boards.
They can support DDR4 memory, new serdes protocol 0x86, eth phy addresses are
different (than previous boards), no. of eth ports are different, etc
Regards
Priyanka
> -Original Message-
> From: Wood Scott-B07421
> Sent:
Hi Bill, Segher,
> I agree with Segher. We already know we have opportunities to do a
> better job with shrink-wrapping (pushing this kind of useless
> activity down past early exits), so having examples of code to look
> at to improve this would be useful.
I'll look out for specific examples. I
Hi Scott,
On 08/08/2015 10:29 AM, Scott Wood wrote:
[Please wrap commit messages at around 74 columns]
Ok, I will when sending a new version.
On Fri, Aug 07, 2015 at 02:58:10PM +0800, Yuanjie Huang wrote:
PowerPC Book3E processor features hardware-supported single instruction
execution, and
On Fri, Aug 07, 2015 at 06:59:58PM +1000, Alexey Kardashevskiy wrote:
>On 08/07/2015 12:01 PM, Wei Yang wrote:
>>On Thu, Aug 06, 2015 at 08:04:58PM +1000, Alexey Kardashevskiy wrote:
>>>On 08/05/2015 11:25 AM, Wei Yang wrote:
In current implementation, when VF BAR is bigger than 64MB, it uses 4
Shilpasri G Bhat writes:
> diff --git a/drivers/cpufreq/powernv-cpufreq.c
> b/drivers/cpufreq/powernv-cpufreq.c
> index d0c18c9..a634199 100644
> --- a/drivers/cpufreq/powernv-cpufreq.c
> +++ b/drivers/cpufreq/powernv-cpufreq.c
> @@ -33,6 +33,7 @@
> #include
> #include
> #include /* Require
On Fri, Aug 07, 2015 at 05:14:41PM +1000, Alexey Kardashevskiy wrote:
>On 08/07/2015 12:24 PM, Wei Yang wrote:
>>On Fri, Aug 07, 2015 at 11:20:10AM +1000, Gavin Shan wrote:
>>>On Thu, Aug 06, 2015 at 10:10:10PM +0800, Wei Yang wrote:
On Thu, Aug 06, 2015 at 02:35:57PM +1000, Gavin Shan wrote:
>
On Sat, 2015-08-08 at 21:17 -0700, Christian Kujau wrote:
> [Adding linux-...@vger.kernel.org]
>
> On Fri, 7 Aug 2015, Christian Kujau wrote:
> > this PowerBook G4 was running 3.16 for a while but now I wanted to upgrade
> > to latest mainline. However, during bootup the following happens:
> >
>
Shilpasri G Bhat writes:
> Add OPAL_MSG_OCC message definition to opal_message_type to receive
> OCC events like reset, load and throttled. Host performance can be
> affected when OCC is reset or OCC throttles the max Pstate.
> We can register to opal_message_notifier to receive OPAL_MSG_OCC type
Hi,
I'm experiencing a regression in EEH that was introduced somewhere
between 4.0 and 4.1.
I have been reproducing this with a CAPI (CXL) card, but the behaviour
isn't CAPI related and the triggering code hasn't changed. CAPI cards
are reprogrammed by PERSTing the slot they sit in, so CAPI expos
On Sun, Aug 9, 2015 at 9:27 AM, Ran Shalit wrote:
> On Thu, Aug 6, 2015 at 6:07 AM, Scott Wood wrote:
>> On Wed, 2015-08-05 at 17:27 +0300, Ran Shalit wrote:
>>> On Wed, Aug 5, 2015 at 9:11 AM, Ran Shalit wrote:
>>> > On Wed, Aug 5, 2015 at 6:56 AM, Ran Shalit wrote:
>>> > > On Wed, Aug 5, 2015
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