On Tue, May 12, 2015 at 09:31:34AM +0800, Wei Yang wrote:
>On Mon, May 11, 2015 at 02:22:38PM +1000, Gavin Shan wrote:
>>On Mon, May 04, 2015 at 03:07:37PM +0800, Wei Yang wrote:
>>>Since FW is not aware of VFs, the restore action for VF should be done in
>> ^^
>> skiboot firmware
>>>ke
On Mon, May 11, 2015 at 02:25:49PM +0800, Wei Yang wrote:
>On Mon, May 11, 2015 at 12:37:07PM +1000, Gavin Shan wrote:
>>On Mon, May 04, 2015 at 03:07:34PM +0800, Wei Yang wrote:
>>
>>Please reorder PATCH[6] with this one because the EEH device is expected
>>to be created before EEH PE.
>
>That's a
On Mon, May 11, 2015 at 01:54:12PM +0800, Wei Yang wrote:
>On Mon, May 11, 2015 at 12:21:04PM +1000, Gavin Shan wrote:
>>On Mon, May 04, 2015 at 03:07:31PM +0800, Wei Yang wrote:
>>>This patch caches the index of a VF in its PF in pci_dn.
>>>
>>
>>At least you can mention the purpose of vf_index to
Architectures like ppc64 [1] need to do special things while clearing
pmd before a collapse. For them this operation is largely different
from a normal hugepage pte clear. Hence add a separate function
to clear pmd before collapse. After this patch pmdp_* functions
operate only on hugepage pte, and
Also move the pmd_trans_huge check to generic code.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc64.h | 4
arch/powerpc/mm/pgtable_64.c | 11 ---
mm/pgtable-generic.c | 1 +
3 files changed, 1 insertion(+), 15 deletions(-)
We have confusing functions to clear pmd, pmd_clear_* and pmd_clear.
Add _huge_ to pmdp_clear functions so that we are clear that they
operate on hugepage pte.
We don't bother about other functions like pmdp_set_wrprotect,
pmdp_clear_flush_young, because they operate on PTE bits and hence
indicate
On 04/10/2015 01:59 PM, Anshuman Khandual wrote:
> This patch series has patches for POWER DSCR fixes, improvements,
> in code documentaion, kernel support user documentation and selftest based
> test cases. It has got five test cases which are derived from Anton's DSCR
> test bucket which ca
Hi ,
On Mon, May 11, 2015 at 2:08 PM, Suman Tripathi wrote:
> This patch adds the arasan sdhci nodes to reuse the of-arasan
> driver for APM X-Gene SoC.
>
> Signed-off-by: Suman Tripathi
> ---
> arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
> arch/arm64/boot/dts/apm/apm-storm.dtsi | 43
>
It is always a headache dealing with different defconfigs
though they only differ in a few places. Hence we are proposing a new
way of writing the defconfig:
1. Define a basic defconfig say mpc85xx_basic_defconfig
2. Spin off as much features as possible from the current mpc85xx_defconfig
a
It is always a headache dealing with different defconfigs
though they only differ in a few places. Hence we are proposing a new
way of writing the defconfig:
1. Define a basic defconfig say mpc85xx_basic_defconfig
2. Spin off as much features as possible from the current mpc85xx_defconfig
a
Before 69111bac42f5 ("powerpc: Replace __get_cpu_var uses"), in
save_mce_event, index got the value of mce_nest_count, and
mce_nest_count was incremented *after* index was set.
However, that patch changed the behaviour so that mce_nest count was
incremented *before* setting index.
This causes an
On Tue, May 12, 2015 at 01:38:50AM +1000, Alexey Kardashevskiy wrote:
>This relies on the fact that a PCI device always has an IOMMU table
>which may not be the case when we get dynamic DMA windows so
>let's use more reliable check for IOMMU group here.
>
>As we do not rely on the table presence he
On Mon, May 11, 2015 at 02:22:38PM +1000, Gavin Shan wrote:
>On Mon, May 04, 2015 at 03:07:37PM +0800, Wei Yang wrote:
>>Since FW is not aware of VFs, the restore action for VF should be done in
> ^^
> skiboot firmware
>>kernel.
>>
>>This patch introduces pnv_eeh_vf_restore_config() for
On Tue, May 12, 2015 at 10:53:29AM +1000, Alexey Kardashevskiy wrote:
>On 05/12/2015 10:03 AM, Gavin Shan wrote:
>>On Mon, May 11, 2015 at 05:02:08PM +1000, Alexey Kardashevskiy wrote:
>>>On 05/11/2015 04:25 PM, Gavin Shan wrote:
On Sat, May 09, 2015 at 10:43:23PM +1000, Alexey Kardashevskiy wr
On 05/12/2015 10:03 AM, Gavin Shan wrote:
On Mon, May 11, 2015 at 05:02:08PM +1000, Alexey Kardashevskiy wrote:
On 05/11/2015 04:25 PM, Gavin Shan wrote:
On Sat, May 09, 2015 at 10:43:23PM +1000, Alexey Kardashevskiy wrote:
On 05/01/2015 04:02 PM, Gavin Shan wrote:
The original code doesn't s
On Mon, May 11, 2015 at 05:17:42PM +1000, Alexey Kardashevskiy wrote:
>On 05/11/2015 04:47 PM, Gavin Shan wrote:
>>On Sun, May 10, 2015 at 12:12:18AM +1000, Alexey Kardashevskiy wrote:
>>>On 05/01/2015 04:02 PM, Gavin Shan wrote:
Function pnv_pci_reset_secondary_bus() is used to reset specified
On Mon, May 11, 2015 at 05:02:08PM +1000, Alexey Kardashevskiy wrote:
>On 05/11/2015 04:25 PM, Gavin Shan wrote:
>>On Sat, May 09, 2015 at 10:43:23PM +1000, Alexey Kardashevskiy wrote:
>>>On 05/01/2015 04:02 PM, Gavin Shan wrote:
The original code doesn't support releasing PEs dynamically, mean
On Mon, 2015-05-11 at 09:34 +0200, w...@the-dreams.de wrote:
> On Mon, May 11, 2015 at 08:14:47AM +1000, Benjamin Herrenschmidt wrote:
> > On Sun, 2015-05-10 at 20:34 +0200, Wolfram Sang wrote:
> > > Okay, so this patch is bogus. I understand now that onyx uses another
> > > codec than TAS, so this
On Monday, May 11, 2015 07:40:41 PM Daniel Lezcano wrote:
> On 05/10/2015 01:15 AM, Rafael J. Wysocki wrote:
> > On Saturday, May 09, 2015 10:33:05 PM Rafael J. Wysocki wrote:
> >> On Saturday, May 09, 2015 10:11:41 PM Rafael J. Wysocki wrote:
> >>> On Saturday, May 09, 2015 11:19:16 AM Preeti U Mu
On Monday, May 11, 2015 04:13:37 PM Sudeep Holla wrote:
>
> On 10/05/15 00:15, Rafael J. Wysocki wrote:
> > On Saturday, May 09, 2015 10:33:05 PM Rafael J. Wysocki wrote:
> >> On Saturday, May 09, 2015 10:11:41 PM Rafael J. Wysocki wrote:
> >>> On Saturday, May 09, 2015 11:19:16 AM Preeti U Murthy
On Monday, May 11, 2015 10:51:02 AM Preeti U Murthy wrote:
> On 05/10/2015 04:45 AM, Rafael J. Wysocki wrote:
> > On Saturday, May 09, 2015 10:33:05 PM Rafael J. Wysocki wrote:
> >> On Saturday, May 09, 2015 10:11:41 PM Rafael J. Wysocki wrote:
> >>> On Saturday, May 09, 2015 11:19:16 AM Preeti U M
On Mon, 11 May 2015 12:09:30 +0530 "Aneesh Kumar K.V"
wrote:
> Architectures like ppc64 [1] need to do special things while clearing
> pmd before a collapse. For them this operation is largely different
> from a normal hugepage pte clear. Hence add a separate function
> to clear pmd before colla
trigg writes:
>> --- a/arch/powerpc/include/asm/opal-api.h
>> +++ b/arch/powerpc/include/asm/opal-api.h
>> @@ -730,6 +730,36 @@ struct opal_i2c_request {
>> __be64 buffer_ra; /* Buffer real address */
>> };
>>
>> +/*
>> + * EPOW status sharing (OPAL and the host)
>> + *
>> +
On Fri, 2015-05-08 at 06:23 +0530, Hemant Kumar wrote:
> For perf to analyze the KVM events like hcalls, we need the
> hypervisor calls and their codes to be exported through uapi.
>
> This patch moves most of the pSeries hcall codes from
> arch/powerpc/include/asm/hvcall.h to
> arch/powerpc/inclu
On Fri, 2015-05-08 at 06:37 +0530, Hemant Kumar wrote:
> From: Srikar Dronamraju
>
> perf kvm can be used to analyze guest exit reasons. This support already
> exists in x86. Hence, porting it to powerpc.
>
> - To trace KVM events :
> perf kvm stat record
> If many guests are running, we ca
On Mon, 11 May 2015, Andrew Morton wrote:
> On Mon, 11 May 2015 10:36:18 -0400 Eric B Munson wrote:
>
> > On Fri, 08 May 2015, Andrew Morton wrote:
> > ...
> >
> > >
> > > Why can't the application mmap only those parts of the file which it
> > > wants and mlock those?
> >
> > There are a numb
Jia Hongtao,
Thanks for sharing your driver. Sorry for the late answer. Please find
couple of comments as follows.
On Fri, Apr 03, 2015 at 03:11:27PM +0800, Jia Hongtao wrote:
> It supports one critical trip point and one passive trip point.
> The cpufreq is used as the cooling device to throttle
On Mon, 11 May 2015 10:36:18 -0400 Eric B Munson wrote:
> On Fri, 08 May 2015, Andrew Morton wrote:
> ...
>
> >
> > Why can't the application mmap only those parts of the file which it
> > wants and mlock those?
>
> There are a number of problems with this approach. The first is it
> presumes
On Fri, 08 May 2015, Andrew Morton wrote:
> On Fri, 8 May 2015 15:33:43 -0400 Eric B Munson wrote:
>
> > mlock() allows a user to control page out of program memory, but this
> > comes at the cost of faulting in the entire mapping when it is
> > allocated. For large mappings where the entire a
On 05/10/2015 01:15 AM, Rafael J. Wysocki wrote:
On Saturday, May 09, 2015 10:33:05 PM Rafael J. Wysocki wrote:
On Saturday, May 09, 2015 10:11:41 PM Rafael J. Wysocki wrote:
On Saturday, May 09, 2015 11:19:16 AM Preeti U Murthy wrote:
Hi Rafael,
On 05/08/2015 07:48 PM, Rafael J. Wysocki wrot
This adds a way for the IOMMU user to know how much a new table will
use so it can be accounted in the locked_vm limit before allocation
happens.
This stores the allocated table size in pnv_pci_ioda2_get_table_size()
so the locked_vm counter can be updated correctly when a table is
being disposed.
This extends iommu_table_group_ops by a set of callbacks to support
dynamic DMA windows management.
create_table() creates a TCE table with specific parameters.
it receives iommu_table_group to know nodeid in order to allocate
TCE table memory closer to the PHB. The exact format of allocated
multi
At the moment writing new TCE value to the IOMMU table fails with EBUSY
if there is a valid entry already. However PAPR specification allows
the guest to write new TCE value without clearing it first.
Another problem this patch is addressing is the use of pool locks for
external IOMMU users such a
This adds create/remove window ioctls to create and remove DMA windows.
sPAPR defines a Dynamic DMA windows capability which allows
para-virtualized guests to create additional DMA windows on a PCI bus.
The existing linux kernels use this new window to map the entire guest
memory and switch to the
Modern IBM POWERPC systems support multiple (currently two) TCE tables
per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
for TCE tables. Right now just one table is supported.
This defines iommu_table_group struct which stores pointers to
iommu_group and iommu_table(s). This rep
The existing implementation accounts the whole DMA window in
the locked_vm counter. This is going to be worse with multiple
containers and huge DMA windows. Also, real-time accounting would requite
additional tracking of accounted pages due to the page size difference -
IOMMU uses 4K pages and syst
At the moment the DMA setup code looks for the "ibm,opal-tce-kill" property
which contains the TCE kill register address. Writes to this register
invalidates TCE cache on IODA/IODA2 hub.
This moves the register address from iommu_table to pnv_ioda_pe as:
1) When we get 2 tables per PE, this regist
TCE tables might get too big in case of 4K IOMMU pages and DDW enabled
on huge guests (hundreds of GB of RAM) so the kernel might be unable to
allocate contiguous chunk of physical memory to store the TCE table.
To address this, POWER8 CPU (actually, IODA2) supports multi-level
TCE tables, up to 5
This moves iommu_table creation to the beginning to make following changes
easier to review. This starts using table parameters from the iommu_table
struct.
This should cause no behavioural change.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
---
Changes:
v9:
* updated commit l
This adds missing locks in iommu_take_ownership()/
iommu_release_ownership().
This marks all pages busy in iommu_table::it_map in order to catch
errors if there is an attempt to use this table while ownership over it
is taken.
This only clears TCE content if there is no page marked busy in it_map
This adds a iommu_table_ops struct and puts pointer to it into
the iommu_table struct. This moves tce_build/tce_free/tce_get/tce_flush
callbacks from ppc_md to the new struct where they really belong to.
This adds the requirement for @it_ops to be initialized before calling
iommu_init_table() to m
This is a pretty mechanical patch to make next patches simpler.
New tce_iommu_unuse_page() helper does put_page() now but it might skip
that after the memory registering patch applied.
As we are here, this removes unnecessary checks for a value returned
by pfn_to_page() as it cannot possibly retu
We are adding support for DMA memory pre-registration to be used in
conjunction with VFIO. The idea is that the userspace which is going to
run a guest may want to pre-register a user space memory region so
it all gets pinned once and never goes away. Having this done,
a hypervisor will not have to
There moves locked pages accounting to helpers.
Later they will be reused for Dynamic DMA windows (DDW).
This reworks debug messages to show the current value and the limit.
This stores the locked pages number in the container so when unlocking
the iommu table pointer won't be needed. This does n
At the moment DMA map/unmap requests are handled irrespective to
the container's state. This allows the user space to pin memory which
it might not be allowed to pin.
This adds checks to MAP/UNMAP that the container is enabled, otherwise
-EPERM is returned.
Signed-off-by: Alexey Kardashevskiy
[a
This checks that the TCE table page size is not bigger that the size of
a page we just pinned and going to put its physical address to the table.
Otherwise the hardware gets unwanted access to physical memory between
the end of the actual page and the end of the aligned up TCE page.
Since compoun
The existing code programmed TVT#0 with some address and then
immediately released that memory.
This makes use of pnv_pci_ioda2_unset_window() and
pnv_pci_ioda2_set_bypass() which do correct resource release and
TVT update.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/
This is to make extended ownership and multiple groups support patches
simpler for review.
This should cause no behavioural change.
Signed-off-by: Alexey Kardashevskiy
[aw: for the vfio related changes]
Acked-by: Alex Williamson
Reviewed-by: David Gibson
---
drivers/vfio/vfio_iommu_spapr_tce.
This makes use of the it_page_size from the iommu_table struct
as page size can differ.
This replaces missing IOMMU_PAGE_SHIFT macro in commented debug code
as recently introduced IOMMU_PAGE_XXX macros do not include
IOMMU_PAGE_SHIFT.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
The iommu_table struct keeps a list of IOMMU groups it is used for.
At the moment there is just a single group attached but further
patches will add TCE table sharing. When sharing is enabled, TCE cache
in each PE needs to be invalidated so does the patch.
This does not change pnv_pci_ioda1_tce_in
Normally a bitmap from the iommu_table is used to track what TCE entry
is in use. Since we are going to use iommu_table without its locks and
do xchg() instead, it becomes essential not to put bits which are not
implied in the direction flag as the old TCE value (more precisely -
the permission bit
This moves page pinning (get_user_pages_fast()/put_page()) code out of
the platform IOMMU code and puts it to VFIO IOMMU driver where it belongs
to as the platform code does not deal with page pinning.
This makes iommu_take_ownership()/iommu_release_ownership() deal with
the IOMMU table bitmap onl
This is a part of moving DMA window programming to an iommu_ops
callback. pnv_pci_ioda2_set_window() takes an iommu_table_group as
a first parameter (not pnv_ioda_pe) as it is going to be used as
a callback for VFIO DDW code.
This adds pnv_pci_ioda2_tvt_invalidate() to invalidate TVT as it is
a go
Before the IOMMU user (VFIO) would take control over the IOMMU table
belonging to a specific IOMMU group. This approach did not allow sharing
tables between IOMMU groups attached to the same container.
This introduces a new IOMMU ownership flavour when the user can not
just control the existing IO
This replaces direct accesses to TCE table with a helper which
returns an TCE entry address. This does not make difference now but will
when multi-level TCE tables get introduces.
No change in behavior is expected.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
---
Changes:
v9:
*
Modern IBM POWERPC systems support multiple (currently two) TCE tables
per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
for TCE tables. Right now just one table is supported.
For IODA, instead of embedding iommu_table, the new iommu_table_group
keeps pointers to those. The iomm
This adds tce_iommu_take_ownership() and tce_iommu_release_ownership
which call in a loop iommu_take_ownership()/iommu_release_ownership()
for every table on the group. As there is just one now, no change in
behaviour is expected.
At the moment the iommu_table struct has a set_bypass() which enabl
This is a part of moving TCE table allocation into an iommu_ops
callback to support multiple IOMMU groups per one VFIO container.
This moves the code which allocates the actual TCE tables to helpers:
pnv_pci_ioda2_table_alloc_pages() and pnv_pci_ioda2_table_free_pages().
These do not allocate/free
At the moment iommu_free_table() only releases memory if
the table was initialized for the platform code use, i.e. it had
it_map initialized (which purpose is to track DMA memory space use).
With dynamic DMA windows, we will need to be able to release
iommu_table even if it was used for VFIO in wh
The pnv_pci_ioda_tce_invalidate() helper invalidates TCE cache. It is
supposed to be called on IODA1/2 and not called on p5ioc2. It receives
start and end host addresses of TCE table.
IODA2 actually needs PCI addresses to invalidate the cache. Those
can be calculated from host addresses but since
The set_iommu_table_base_and_group() name suggests that the function
sets table base and add a device to an IOMMU group. However actual
table base setting happens in pnv_pci_ioda_dma_dev_setup().
The actual purpose for table base setting is to put some reference
into a device so later iommu_add_de
The existing code has 3 calls to iommu_register_group() and
all 3 branches actually cover all possible cases.
This replaces 3 calls with one and moves the registration earlier;
the latter will make more sense when we add TCE table sharing.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/pl
This relies on the fact that a PCI device always has an IOMMU table
which may not be the case when we get dynamic DMA windows so
let's use more reliable check for IOMMU group here.
As we do not rely on the table presence here, remove the workaround
from pnv_pci_ioda2_set_bypass(); also remove the
So far an iommu_table lifetime was the same as PE. Dynamic DMA windows
will change this and iommu_free_table() will not always require
the group to be released.
This moves iommu_group_put() out of iommu_free_table().
This adds a iommu_pseries_free_table() helper which does
iommu_group_put() and i
This enables sPAPR defined feature called Dynamic DMA windows (DDW).
Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
where devices are allowed to do DMA. These ranges are called DMA windows.
By default, there is a single DMA window, 1 or 2GB big, mapped at zero
on a PC
On 10/05/15 00:15, Rafael J. Wysocki wrote:
On Saturday, May 09, 2015 10:33:05 PM Rafael J. Wysocki wrote:
On Saturday, May 09, 2015 10:11:41 PM Rafael J. Wysocki wrote:
On Saturday, May 09, 2015 11:19:16 AM Preeti U Murthy wrote:
Hi Rafael,
On 05/08/2015 07:48 PM, Rafael J. Wysocki wrote:
On Fri, 08 May 2015, Andrew Morton wrote:
> On Fri, 8 May 2015 16:06:10 -0400 Eric B Munson wrote:
>
> > On Fri, 08 May 2015, Andrew Morton wrote:
> >
> > > On Fri, 8 May 2015 15:33:43 -0400 Eric B Munson
> > > wrote:
> > >
> > > > mlock() allows a user to control page out of program memory
When sai works on master mode, set its bit clock and frame clock.
SAI has 4 MCLK source, bus clock, MCLK1, MCLK2 and MCLK3. fsl_sai_set_bclk
will select proper MCLK source, then calculate and set the bit clock divider.
After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and add
hw_fr
On 11/05/2015 12:31, Michael Ellerman wrote:
> On Tue, 2015-05-05 at 15:30:21 UTC, Laurent Dufour wrote:
>> The commit 8170a83f15ee ("powerpc: Wireup the kcmp syscall to sys_ni") has
>> disabled the kcmp syscall for powerpc. This has been done due to the use
>> of unsigned long parameters which ma
This patch introduces some functions for converting cputime to timespec64 and
back,
that repalce the timespec type with timespec64 type, as well as for arch/s390
and
arch/powerpc architecture.
And these new methods will replace the old
cputime_to_timespec/timespec_to_cputime
function to ready f
This patch series changes the 32-bit time type (timespec/itimerspec) to the
64-bit one
(timespec64/itimerspec64), since 32-bit time types will break in the year 2038.
This patch series introduces new methods with timespec64/itimerspec64 type,
and removes the old ones with timespec/itimerspec type
This patch series changes the 32-bit time type (timespec/itimerspec) to the
64-bit one
(timespec64/itimerspec64), since 32-bit time types will break in the year 2038.
This patch series introduces new methods with timespec64/itimerspec64 type,
and removes the old ones with timespec/itimerspec type
Add SAI master mode support.
Add tdm slots operation for SAI master mode.
Add 12kHz, 24kHz, 176.4kHz and 192kHz sample rate support.
Zidan Wang (3):
SoC: fsl_sai: add sai master mode support
ASoC: fsl_sai: Add tdm slots operation for SAI master mode
ASoC: fsl_sai: add 12kHz, 24kHz, 176.4kHz
Add tdm slot operation for SAI master mode. When using SAI as master
mode, we should use set_tdm_slot() helper function to set tdm slots
in machine driver, or it will using default value of slots and slot
width.
SAI will generate BCLK depends on sample rate, slots and slot width.
And there may be
On 05/11/2015 02:31 PM, Vipin K Parashar wrote:
On 05/11/2015 12:19 PM, Michael Ellerman wrote:
On Thu, 2015-05-07 at 15:00 +0530, Vipin K Parashar wrote:
This patch adds support for FSP EPOW (Early Power Off Warning) and
DPO (Delayed Power Off) events support for PowerNV platform. EPOW
even
Normally we don't support 12kHz, 24kHz in audio driver, alsa didn't
have formal definition of 12kHz, 24kHz, but alsa supply a way to
support these sample rates. And add 176.4kHz and 192kHz support.
Signed-off-by: Zidan Wang
---
sound/soc/fsl/fsl_sai.c | 24 +---
1 file change
On Tue, 2015-05-05 at 15:30:21 UTC, Laurent Dufour wrote:
> The commit 8170a83f15ee ("powerpc: Wireup the kcmp syscall to sys_ni") has
> disabled the kcmp syscall for powerpc. This has been done due to the use
> of unsigned long parameters which may require a dedicated wrapper to handle
> 32bit pr
On Thu, 2015-30-04 at 03:04:51 UTC, Sukadev Bhattiprolu wrote:
> We currently try to register the 24x7 PMU unconditionally. Not all
> Power systems support 24x7 counters (eg: Power7). On these systems
> we get a backtrace during boot when trying to register the 24x7 PMU.
>
> Check if the hyperviso
Stable folks please ignore this patch.
Comments below.
On Mon, 2015-11-05 at 00:48:32 UTC, Daniel Axtens wrote:
> Before 69111bac42f5 ("powerpc: Replace __get_cpu_var uses"), in
> save_mce_event, index got the value of mce_nest_count, and
> mce_nest_count was incremented *after* index was set.
>
On Thu, 2015-07-05 at 03:16:15 UTC, Alistair Popple wrote:
> diff --git a/arch/powerpc/platforms/powernv/opal.c
> b/arch/powerpc/platforms/powernv/opal.c
> index 4399ff2..0196220 100644
> --- a/arch/powerpc/platforms/powernv/opal.c
> +++ b/arch/powerpc/platforms/powernv/opal.c
> @@ -362,33 +362,34
On 05/11/2015 12:19 PM, Michael Ellerman wrote:
On Thu, 2015-05-07 at 15:00 +0530, Vipin K Parashar wrote:
This patch adds support for FSP EPOW (Early Power Off Warning) and
DPO (Delayed Power Off) events support for PowerNV platform. EPOW events
are generated by SPCN/FSP due to various critic
"Kirill A. Shutemov" writes:
> On Mon, May 11, 2015 at 12:09:30PM +0530, Aneesh Kumar K.V wrote:
>> Architectures like ppc64 [1] need to do special things while clearing
>> pmd before a collapse. For them this operation is largely different
>> from a normal hugepage pte clear. Hence add a separat
"Kirill A. Shutemov" writes:
> On Mon, May 11, 2015 at 11:56:01AM +0530, Aneesh Kumar K.V wrote:
>> Serialize against find_linux_pte_or_hugepte which does lock-less
>> lookup in page tables with local interrupts disabled. For huge pages
>> it casts pmd_t to pte_t. Since format of pte_t is differe
The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk.
This patch adds the support to disable SDR104/SDR50/DDR50 based on
reading the capability register 0.
Signed-off-by: Suman Tripathi
---
drivers/mmc/host/sdhci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --gi
This patch adds the arasan sdhci nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 +
2 files changed, 47 insertions(+)
diff --g
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI
controller.
v1 change:
* Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping.
v2 change:
* Drop the IOMMU support and switching to PIO mode for arasan.
controller integrated inside APM X-Gene SoC.
v3 change:
* Change t
Pstore only supports one backend at a time. The preferred
pstore backend is set by passing the pstore.backend=
argument to the kernel at boot time. Currently, while trying
to register with pstore, nvram throws an error message even
when "pstore.backend != nvram", which is unnecessary. This
patch re
On Mon, May 11, 2015 at 11:56:01AM +0530, Aneesh Kumar K.V wrote:
> Serialize against find_linux_pte_or_hugepte which does lock-less
> lookup in page tables with local interrupts disabled. For huge pages
> it casts pmd_t to pte_t. Since format of pte_t is different from
> pmd_t we want to prevent t
On Sat, May 09, 2015 at 09:59:25AM +1000, Alexey Kardashevskiy wrote:
>On 05/01/2015 04:02 PM, Gavin Shan wrote:
>>The series of patches intend to support PCI slot for PowerPC PowerNV platform,
>>which is running on top of skiboot firmware. The patchset requires
>>corresponding
>>changes from skib
On Sun, May 10, 2015 at 01:54:31AM +1000, Alexey Kardashevskiy wrote:
>On 05/01/2015 04:03 PM, Gavin Shan wrote:
>>The patch intends to add standalone driver to support PCI hotplug
>>for PowerPC PowerNV platform, which runs on top of skiboot firmware.
>>The firmware identified hotpluggable slots an
On Mon, May 11, 2015 at 08:14:47AM +1000, Benjamin Herrenschmidt wrote:
> On Sun, 2015-05-10 at 20:34 +0200, Wolfram Sang wrote:
> > Okay, so this patch is bogus. I understand now that onyx uses another
> > codec than TAS, so this change will regress on other machines.
> > However,
> > it shows tha
On Sun, May 10, 2015 at 01:08:28AM +1000, Alexey Kardashevskiy wrote:
>On 05/01/2015 04:03 PM, Gavin Shan wrote:
>>The eeh_dev is always created based on pci_dn, but with initcall
>>supported by core_initcall_sync(). The patch creates eeh_dev
>>when pci_dn is created, indicating they have same life
On Sun, May 10, 2015 at 12:55:51AM +1000, Alexey Kardashevskiy wrote:
>On 05/01/2015 04:03 PM, Gavin Shan wrote:
>>The pci_dn instances are allocated from memblock or bootmem when
>>creating PCI controller (hoses) in setup_arch(). The PCI hotplug,
>>which will be supported by proceeding patches, wi
On Thu, May 07, 2015 at 01:49:11PM -0400, Dan Streetman wrote:
>
> v3 changes the sw and hw crypto drivers to use the same alg name "842",
> and different driver names, "842-generic" and "842-nx"
All applied. Thanks a lot!
--
Email: Herbert Xu
Home Page: http://gondor.apana.org.au/~herbert/
PGP
On Sun, May 10, 2015 at 12:30:07AM +1000, Alexey Kardashevskiy wrote:
>On 05/01/2015 04:03 PM, Gavin Shan wrote:
>>We might not get some PCI slot information (e.g. power status)
>>immediately by OPAL API. Instead, opal_pci_poll() need to be called
>>for the required information.
>>
>>The patch intr
On 05/11/2015 04:47 PM, Gavin Shan wrote:
On Sun, May 10, 2015 at 12:12:18AM +1000, Alexey Kardashevskiy wrote:
On 05/01/2015 04:02 PM, Gavin Shan wrote:
Function pnv_pci_reset_secondary_bus() is used to reset specified
PCI bus, which is leaded by root complex or PCI bridge. That means
the func
On 05/11/2015 04:45 PM, Gavin Shan wrote:
On Sat, May 09, 2015 at 11:41:05PM +1000, Alexey Kardashevskiy wrote:
On 05/01/2015 04:02 PM, Gavin Shan wrote:
For PowerNV platform, running on top of skiboot, all PE level reset
should be routed to firmware if the bridge of the PE primary bus has
devi
On 2015-05-11 10:48:32 Mon, Daniel Axtens wrote:
> Before 69111bac42f5 ("powerpc: Replace __get_cpu_var uses"), in
> save_mce_event, index got the value of mce_nest_count, and
> mce_nest_count was incremented *after* index was set.
>
> However, that patch changed the behaviour so that mce_nest cou
Hi Joel,
Thanks for review. My comments below.
On 05/08/2015 06:56 AM, Joel Stanley wrote:
Hello Vipin,
On Thu, May 7, 2015 at 7:00 PM, Vipin K Parashar
wrote:
This patch adds support for FSP EPOW (Early Power Off Warning) and
DPO (Delayed Power Off) events support for PowerNV plat
On 05/11/2015 04:25 PM, Gavin Shan wrote:
On Sat, May 09, 2015 at 10:43:23PM +1000, Alexey Kardashevskiy wrote:
On 05/01/2015 04:02 PM, Gavin Shan wrote:
The original code doesn't support releasing PEs dynamically, meaning
that PE and the associated resources (IO, M32, M64 and DMA) can't
be rel
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