On Thu, 2015-03-12 at 10:46 -0500, Bhushan Bharat-R65777 wrote:
>
>
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Thursday, March 12, 2015 4:53 AM
> > To: Bhushan Bharat-R65777
> > Cc: linuxppc-...@ozlabs.org
> > Subject: Re: [PATCH 3/4 RFC] fsl/msi: Add MSI bank allocation
The 'arg' argument to copy_thread() is only ever used when forking a new
kernel thread. Hence, rename it to 'kthread_arg' for clarity (and consistency
with do_fork() and other arch-specific implementations of copy_thread()).
Signed-off-by: Alex Dowad
---
arch/powerpc/kernel/process.c | 9 +++
Hi David,
On Fri, 13 Mar 2015 14:18:10 + David Laight wrote:
>
> From: Stephen Rothwell
> > This runs a bit faster and removes another use of perl from
> > the kernel build.
> ...
> > diff --git a/arch/powerpc/relocs_check.sh b/arch/powerpc/relocs_check.sh
> > new file mode 100755
> > index 0
On Wed, 2015-03-11 at 17:34 +1100, Gavin Shan wrote:
> The patch adds one more EEH sub-command (VFIO_EEH_PE_INJECT_ERR)
> to inject the specified EEH error, which is represented by
> (struct vfio_eeh_pe_err), to the indicated PE for testing purpose.
>
> Signed-off-by: Gavin Shan
> ---
> Document
On Wed, 2015-03-11 at 17:34 +1100, Gavin Shan wrote:
> The patch defines PCI error types and functions in eeh.h and
> exports function eeh_pe_inject_err(), which will be called by
> VFIO driver to inject the specified PCI error to the indicated
> PE for testing purpose.
>
> Signed-off-by: Gavin Sh
On Thu, 2015-03-12 at 15:21 +1100, David Gibson wrote:
> On Thu, Mar 12, 2015 at 02:16:42PM +1100, Gavin Shan wrote:
> > On Thu, Mar 12, 2015 at 11:57:21AM +1100, David Gibson wrote:
> > >On Wed, Mar 11, 2015 at 05:34:11PM +1100, Gavin Shan wrote:
> > >> The patch adds one more EEH sub-command (VFI
On Fri, 2015-03-13 at 17:38 +1100, Michael Ellerman wrote:
> On Fri, 2015-03-13 at 15:39 +1100, Michael Ellerman wrote:
> > We currently have a "special" syscall for switching endianness. This is
> > syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall
> > exception entry.
> >
From: Stephen Rothwell
> This runs a bit faster and removes another use of perl from
> the kernel build.
...
> diff --git a/arch/powerpc/relocs_check.sh b/arch/powerpc/relocs_check.sh
> new file mode 100755
> index ..182eae9cc40d
> --- /dev/null
> +++ b/arch/powerpc/relocs_check.sh
> @@
Hi Horia,
On Wed, Mar 11, 2015 at 11:48 AM, Horia Geantă
wrote:
>
> While here: note that xts-talitos supports only two key lengths - 256
> and 512 bits. There are tcrypt speed tests that check also for 384-bit
> keys (which is out-of-spec, but still...), leading to a "Key Size Error"
> - see bel
(2015/03/13 5:24), Arnaldo Carvalho de Melo wrote:
> Em Mon, Dec 15, 2014 at 08:20:32PM +0530, Naveen N. Rao escreveu:
>> Currently, perf probe considers patterns including a '.' to be a file.
>> However, this causes problems on powerpc ABIv1 where all functions have
>> a leading '.':
>>
>> $ per
On 12 March 2015 at 22:54, Rob Herring wrote:
> On Wed, Mar 11, 2015 at 11:00 AM, Ard Biesheuvel
> wrote:
>> This splits off the reservation of the memory occupied by the FDT
>> binary itself from the processing of the memory reservations it
>> contains. This is necessary because the physical add
On Fri, 13 Mar 2015 20:42:03 +1100
Alexey Kardashevskiy wrote:
> The value returned by virtio_vring_size() is used to allocate memory
> for vring. The used descriptor list (array of vring_used_elem) is
> counted by the header - vring_used struct - is not.
>
> This fixes virtio_vring_size() to re
Alexey Kardashevskiy writes:
> The value returned by virtio_vring_size() is used to allocate memory
> for vring. The used descriptor list (array of vring_used_elem) is
> counted by the header - vring_used struct - is not.
>
> This fixes virtio_vring_size() to return the correct size.
> At the mom
Hi Wolfram,
Based on your patch:
"[RFC V2 04/12] i2c: opal: make use of the new infrastructure for quirks"
From: Neelesh Gupta
Subject: [PATCH] i2c: opal: Update quirk flags to do write-then-anything
Support write-then-anything in the case of 2 i2c messages
for i2c transfer.
Signed-off-by: N
The value returned by virtio_vring_size() is used to allocate memory
for vring. The used descriptor list (array of vring_used_elem) is
counted by the header - vring_used struct - is not.
This fixes virtio_vring_size() to return the correct size.
At the moment rings are quite small (256) and alloca
Alexey Kardashevskiy writes:
> The value returned by virtio_vring_size() is used to allocate memory
> for vring. The used descriptor list (array of vring_used_elem) is
> counted by the header - vring_used struct - is not.
>
> This fixes virtio_vring_size() to return the correct size.
> At the mom
Alexey Kardashevskiy writes:
> Every caller of SLOF_alloc_mem_aligned() assumes the size is the first
> argument while it is not.
>
> This switches align and size and fixes random memory corruptions.
>
> This is grep for SLOF_alloc_mem_aligned with this patch applied:
>
> include/helpers.h|27| ex
The value returned by virtio_vring_size() is used to allocate memory
for vring. The used descriptor list (array of vring_used_elem) is
counted by the header - vring_used struct - is not.
This fixes virtio_vring_size() to return the correct size.
At the moment rings are quite small (256) and alloca
Every caller of SLOF_alloc_mem_aligned() assumes the size is the first
argument while it is not.
This switches align and size and fixes random memory corruptions.
This is grep for SLOF_alloc_mem_aligned with this patch applied:
include/helpers.h|27| extern void *SLOF_alloc_mem_aligned(long size,
At the moment only one group per container is supported.
POWER8 CPUs have more flexible design and allows naving 2 TCE tables per
IOMMU group so we can relax this limitation and support multiple groups
per container.
This adds TCE table descriptors to a container and uses iommu_table_group_ops
to
The pnv_pci_ioda_tce_invalidate() helper invalidates TCE cache. It is
supposed to be called on IODA1/2 and not called on p5ioc2. It receives
start and end host addresses of TCE table. This approach makes it possible
to get pnv_pci_ioda_tce_invalidate() unintentionally called on p5ioc2.
Another issu
This is a part of moving DMA window programming to an iommu_ops
callback.
This is a mechanical patch.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 85 ---
1 file changed, 56 insertions(+), 29 deletions(-)
diff --git a/arch/powe
TCE tables might get too big in case of 4K IOMMU pages and DDW enabled
on huge guests (hundreds of GB of RAM) so the kernel might be unable to
allocate contiguous chunk of physical memory to store the TCE table.
To address this, POWER8 CPU (actually, IODA2) supports multi-level TCE tables,
up to 5
The existing IOMMU requires VFIO_IOMMU_ENABLE call to enable actual use
of the container (i.e. call DMA map/unmap) and this is where we check
the rlimit for locked pages. It assumes that only as much memory
as a default DMA window can be mapped. Every DMA map/unmap request will
do pinning/unpinning
This changes few functions to receive a iommu_table_group pointer
rather than PE as they are going to be a part of upcoming
iommu_table_group_ops callback set.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 13 -
1 file changed, 8 insertions(+), 5
This replaces iommu_take_ownership()/iommu_release_ownership() calls
with the callback calls and it is up to the platform code to call
iommu_take_ownership()/iommu_release_ownership() if needed.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h| 4 +--
arch/powerpc/ke
This adds a iommu_table_ops struct and puts pointer to it into
the iommu_table struct. This moves tce_build/tce_free/tce_get/tce_flush
callbacks from ppc_md to the new struct where they really belong to.
This adds the requirement for @it_ops to be initialized before calling
iommu_init_table() to m
This is to make extended ownership and multiple groups support patches
simpler for review.
This is a mechanical patch.
Signed-off-by: Alexey Kardashevskiy
---
drivers/vfio/vfio_iommu_spapr_tce.c | 38 ++---
1 file changed, 23 insertions(+), 15 deletions(-)
diff
This moves iommu_table creation to the beginning. This is a mechanical
patch.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 30 --
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-
At the moment DMA map/unmap requests are handled irrespective to
the container's state. This allows the user space to pin memory which
it might not be allowed to pin.
This adds checks to MAP/UNMAP that the container is enabled, otherwise
-EPERM is returned.
Signed-off-by: Alexey Kardashevskiy
--
This adds create/remove window ioctls to create and remove DMA windows.
sPAPR defines a Dynamic DMA windows capability which allows
para-virtualized guests to create additional DMA windows on a PCI bus.
The existing linux kernels use this new window to map the entire guest
memory and switch to the
This extends iommu_table_group_ops by a set of callbacks to support
dynamic DMA windows management.
query() returns IOMMU capabilities such as default DMA window address and
supported number of DMA windows and TCE table levels.
create_table() creates a TCE table with specific parameters.
it recei
Modern IBM POWERPC systems support multiple (currently two) TCE tables
per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
for TCE tables. Right now just one table is supported.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h| 18 +++--
arch
This replaces multiple calls of kzalloc_node() with a new
iommu_table_alloc() helper. Right now it calls kzalloc_node() but
later it will be modified to allocate a iommu_table_group struct with
a single iommu_table in it.
Later the helper will allocate a iommu_table_group struct which embeds
the i
There moves locked pages accounting to helpers.
Later they will be reused for Dynamic DMA windows (DDW).
This reworks debug messages to show the current value and the limit.
This stores the locked pages number in the container so when unlocking
the iommu table pointer won't be needed. This does n
Normally a bitmap from the iommu_table is used to track what TCE entry
is in use. Since we are going to use iommu_table without its locks and
do xchg() instead, it becomes essential not to put bits which are not
implied in the direction flag.
This adds iommu_direction_to_tce_perm() (its counterpar
At the moment the iommu_table struct has a set_bypass() which enables/
disables DMA bypass on IODA2 PHB. This is exposed to POWERPC IOMMU code
which calls this callback when external IOMMU users such as VFIO are
about to get over a PHB.
The set_bypass() callback is not really an iommu_table functi
This is a pretty mechanical patch to make next patches simpler.
New tce_iommu_unuse_page() helper does put_page() now but it might skip
that after the memory registering patch applied.
As we are here, this removes unnecessary checks for a value returned
by pfn_to_page() as it cannot possibly retu
This is a part of moving TCE table allocation into an iommu_ops
callback to support multiple IOMMU groups per one VFIO container.
This enforce window size to be a power of two.
This is a pretty mechanical patch.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c
Before the IOMMU user (VFIO) would take control over the IOMMU table
belonging to a specific IOMMU group. This approach did not allow sharing
tables between IOMMU groups attached to the same container.
This introduces a new IOMMU ownership flavour when the user can not
just control the existing IO
The existing implementation accounts the whole DMA window in
the locked_vm counter which is going to be even worse with multiple
containers and huge DMA windows.
This introduces 2 ioctls to register/unregister DMA memory which
receive user space address and size of a memory region which
needs to b
At the moment writing new TCE value to the IOMMU table fails with EBUSY
if there is a valid entry already. However PAPR specification allows
the guest to write new TCE value without clearing it first.
Another problem this patch is addressing is the use of pool locks for
external IOMMU users such a
The iommu_free_table helper release memory it is using (the TCE table and
@it_map) and release the iommu_table struct as well. We might not want
the very last step as we store iommu_table in parent structures.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h | 1 +
arch/
This adds missing locks in iommu_take_ownership()/
iommu_release_ownership().
This marks all pages busy in iommu_table::it_map in order to catch
errors if there is an attempt to use this table while ownership over it
is taken.
This only clears TCE content if there is no page marked busy in it_map
This checks that the TCE table page size is not bigger that the size of
a page we just pinned and going to put its physical address to the table.
Otherwise the hardware gets unwanted access to physical memory between
the end of the actual page and the end of the aligned up TCE page.
Since compoun
This moves page pinning (get_user_pages_fast()/put_page()) code out of
the platform IOMMU code and puts it to VFIO IOMMU driver where it belongs
to as the platform code does not deal with page pinning.
This makes iommu_take_ownership()/iommu_release_ownership() deal with
the IOMMU table bitmap onl
This clears the TCE table when a container is being closed as this is
a good thing to leave the table clean before passing the ownership
back to the host kernel.
Signed-off-by: Alexey Kardashevskiy
---
drivers/vfio/vfio_iommu_spapr_tce.c | 14 +++---
1 file changed, 11 insertions(+), 3 d
This makes use of the it_page_size from the iommu_table struct
as page size can differ.
This replaces missing IOMMU_PAGE_SHIFT macro in commented debug code
as recently introduced IOMMU_PAGE_XXX macros do not include
IOMMU_PAGE_SHIFT.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
This enables sPAPR defined feature called Dynamic DMA windows (DDW).
Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
where devices are allowed to do DMA. These ranges are called DMA windows.
By default, there is a single DMA window, 1 or 2GB big, mapped at zero
on a PCI
On Fri, 2015-03-13 at 00:10 -0700, Ram Pai wrote:
> On Fri, Mar 13, 2015 at 03:39:24PM +1100, Michael Ellerman wrote:
> > This adds a test of the switch_endian() syscall we added in the previous
> > commit.
> >
> > We test it by calling the endian switch syscall, and then executing some
> > code i
On Fri, 2015-03-13 at 18:09 +1100, Michael Ellerman wrote:
> On Thu, 2015-03-12 at 22:13 +1100, Benjamin Herrenschmidt wrote:
> > On Thu, 2015-03-12 at 18:55 +0800, Kevin Hao wrote:
> > > I know Torsten Duwe has tried to add the ticket spinlock for powerpc
> > > one year ago [1]. But it make no pro
On Fri, Mar 13, 2015 at 03:39:24PM +1100, Michael Ellerman wrote:
> This adds a test of the switch_endian() syscall we added in the previous
> commit.
>
> We test it by calling the endian switch syscall, and then executing some
> code in the other endian to check everything went as expected. That
On Thu, 2015-03-12 at 22:13 +1100, Benjamin Herrenschmidt wrote:
> On Thu, 2015-03-12 at 18:55 +0800, Kevin Hao wrote:
> > I know Torsten Duwe has tried to add the ticket spinlock for powerpc
> > one year ago [1]. But it make no progress due to the conflict between
> > PPC_SPLPAR and lockref. We st
On Fri, 2015-03-13 at 14:09 +0800, Kevin Hao wrote:
> On Thu, Mar 12, 2015 at 04:24:10PM +0100, Torsten Duwe wrote:
> > But generally, which platforms would benefit most from this change?
>
> In theory, the more cpus the platform has, the more serious the thundering
> herd problem is. So the lates
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