On 10/17/2014 01:00 AM, kernelf...@gmail.com wrote:
> Signed-off-by: Liu Ping Fan
> ---
> arch/powerpc/kvm/Kconfig | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig
> index 602eb51..de38566 100644
> --- a/arch/powerpc/kvm/Kconfig
> +
On 10/17/2014 12:59 AM, kernelf...@gmail.com wrote:
> (This is a place holder patch.)
> We need to store the time base for host on secondary hwthread.
> Later when switching back, we need to reprogram it with elapse
> time.
>
> Signed-off-by: Liu Ping Fan
> ---
> arch/powerpc/kvm/book3s_hv_rmhan
On Mon, 2014-27-10 at 04:24:35 UTC, Ian Munsie wrote:
> From: Ian Munsie
>
> In certain circumstances the PSL can send an interrupt for a segment
Define PSL before using it please.
> miss that the kernel has already handled. This can happen if multiple
> translations for the same segment are qu
On 10/17/2014 12:59 AM, kernelf...@gmail.com wrote:
> The secondary thread can only jump back to host until primary has set
> up the env. Add host_ready field in kvm_vcore to sync this action.
Do we need to do this? We already synchronize among the sibling threads
when there is a need to enter the
On 10/09/2014 05:18 PM, Anshuman Khandual wrote:
> This patch enables support for hardware instruction breakpoints
> on POWER8 with the help of a new register CIABR (Completed
> Instruction Address Breakpoint Register). With this patch, single
> hardware instruction breakpoint can be added and clea
On 10/17/2014 12:59 AM, kernelf...@gmail.com wrote:
> To enter guest, primary hwtherad schedules the stopper func on
> secondary threads and force them into NAP mode.
> When exit to host,secondary threads hardcode to restore the stack,
> then switch back to the stopper func, i.e host.
>
> Signed-o
Hi Liu,
On 10/17/2014 12:59 AM, kernelf...@gmail.com wrote:
> Nowadays, powerKVM runs with secondary hwthread offline. Although
> we can make all secondary hwthread online later, we still preserve
> this behavior for dedicated KVM env. Achieve this by setting
> paca->online as false.
>
> Signed-o
On 10/17/2014 12:59 AM, kernelf...@gmail.com wrote:
> (This patch is a place holder.)
>
> If there is only one vcpu thread is ready(the other vcpu thread can
> wait for it to execute), the primary thread can enter tickless mode,
We do not configure NOHZ_FULL to y by default. Hence no thread would
From: Ian Munsie
In certain circumstances the PSL can send an interrupt for a segment
miss that the kernel has already handled. This can happen if multiple
translations for the same segment are queued in the PSL before the
kernel has restarted the first translation.
The CXL driver did not expect
Hi Liu,
On 10/17/2014 12:59 AM, kernelf...@gmail.com wrote:
> When kvm is enabled on a core, we migrate all external irq to primary
> thread. Since currently, the kvmirq logic is handled by the primary
> hwthread.
>
> Todo: this patch lacks re-enable of irqbalance when kvm is disable on
> the cor
> -Original Message-
> From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> Sent: Tuesday, October 21, 2014 5:04 PM
> To: Tang Yuantian-B29983
> Cc: Rafael J. Wysocki; Linux Kernel Mailing List; linux...@vger.kernel.org;
> linuxppc-...@ozlabs.org
> Subject: Re: [PATCH] cpufreq: qoriq: Mak
On Fri, 2014-10-24 at 15:30 +0100, Lorenzo Pieralisi wrote:
> On Tue, Oct 14, 2014 at 08:53:00AM +0100, Preeti U Murthy wrote:
> > We hard code the metrics relevant for cpuidle states in the kernel today.
> > Instead pick them up from the device tree so that they remain relevant
> > and updated for
On 2014/10/25 21:04, Ralf Baechle wrote:
> On Wed, Oct 15, 2014 at 11:07:04AM +0800, Yijing Wang wrote:
>
>> +static inline struct msi_chip *pci_msi_chip(struct pci_bus *bus)
>> +{
>> +struct pci_controller *control = (struct pci_controller *)bus->sysdata;
>
> bus->sysdata is void * so this c
Hello,
On Mon, Oct 27, 2014 at 07:50:41AM +1100, Benjamin Herrenschmidt wrote:
> On Fri, 2014-10-24 at 09:22 -0700, James Bottomley wrote:
>
> > Parisc does this. As soon as one CPU issues a TLB purge, it's broadcast
> > to all the CPUs on the inter-CPU bus. The next instruction isn't
> > execu
On Fri, 2014-10-24 at 09:22 -0700, James Bottomley wrote:
> Parisc does this. As soon as one CPU issues a TLB purge, it's broadcast
> to all the CPUs on the inter-CPU bus. The next instruction isn't
> executed until they respond.
>
> But this is only for our CPU TLB. There's no other external
Cc: Matt Evans
Signed-off-by: Denis Kirjanov
---
arch/powerpc/include/asm/ppc-opcode.h | 1 +
arch/powerpc/net/bpf_jit.h| 7 +++
arch/powerpc/net/bpf_jit_comp.c | 5 +
3 files changed, 13 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/
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