MADV_FREE needs pmd_dirty and pmd_mkclean for detecting recent
overwrite of the contents since MADV_FREE syscall is called for
THP page.
This patch adds pmd_dirty and pmd_mkclean for THP page MADV_FREE
support.
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: "Aneesh Kumar K.V"
Cc: linuxppc-d
On Fri, 2014-07-18 at 11:41 +0930, Joel Stanley wrote:
> These processors do not currently support doorbell IPIs, so remove them
> from the feature list if we are at DD 1.xx for the 0x004d part.
We GAed with DD2.1 and generally we don't upstream anything that isn't
GAed. Plus, if you wanna go dow
Hey again Ben,
I am hitting quite a few fix mes in this file. I am wondering how you
would like me to fix them.
Cheers Nick
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No code changes, just split it out to a function so that with the addition
of micro partition prefetch buffer allocation (in subsequent patch) looks
neater and doesn't require excessive indentation.
Signed-off-by: Stewart Smith
---
arch/powerpc/kvm/book3s_hv.c | 31 +---
The POWER8 processor has a Micro Partition Prefetch Engine, which is
a fancy way of saying "has way to store and load contents of L2 or
L2+MRU way of L3 cache". We initiate the storing of the log (list of
addresses) using the logmpp instruction and start restore by writing
to a SPR.
The logmpp ins
changes since v3:
- use kvmppc namespace
- MPP_BUFFER_ORDER of 3 not 4, as we only need 32k and it's already 32k aligned
- split out kvmppc_vcore_create in separate patch
- give a variable a better name: s/tmp/mpp_addr/
- logmpp becomes static inline function
Stewart Smith (2):
Split out struct
Alexander Graf writes:
>> diff --git a/arch/powerpc/include/asm/kvm_host.h
>> b/arch/powerpc/include/asm/kvm_host.h
>> index 1eaea2d..5769497 100644
>> --- a/arch/powerpc/include/asm/kvm_host.h
>> +++ b/arch/powerpc/include/asm/kvm_host.h
>> @@ -305,6 +305,8 @@ struct kvmppc_vcore {
>> u32 a
Paul Mackerras writes:
> On Thu, Jul 17, 2014 at 01:19:57PM +1000, Stewart Smith wrote:
>
>> The POWER8 processor has a Micro Partition Prefetch Engine, which is
>> a fancy way of saying "has way to store and load contents of L2 or
>> L2+MRU way of L3 cache". We initiate the storing of the log (li
Hey Ben,
Me and Steven have discussed that the allyesconfig build is still
failing.I seem to hitting this in the main branch too and not the
linux next tree .
Furthermore I will attach my log of my build failing as I am cross
compiling on an Intel Sandy Bridge i5 2500k at 4.5ghz. Perhaps we can
cle
> -Original Message-
> From: Nicolin Chen [mailto:nicoleots...@gmail.com]
> Sent: Thursday, July 17, 2014 9:22 PM
> To: broo...@kernel.org
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; alsa-
> de...@alsa-project.org; ti...@tabi.org; Xiubo Li-B47053; Wang Shengjiu-B02247
These processors do not currently support doorbell IPIs, so remove them
from the feature list if we are at DD 1.xx for the 0x004d part.
This fixes a regression caused by d4e58e5928f8 (powerpc/powernv: Enable
POWER8 doorbell IPIs). With that patch the kernel would hang at boot
when calling smp_call
On Thu, Jul 17, 2014 at 01:19:57PM +1000, Stewart Smith wrote:
> The POWER8 processor has a Micro Partition Prefetch Engine, which is
> a fancy way of saying "has way to store and load contents of L2 or
> L2+MRU way of L3 cache". We initiate the storing of the log (list of
> addresses) using the l
On 17/07/14 21:14, Michael Neuling wrote:
>
> On Jul 17, 2014 9:11 PM, "Benjamin Herrenschmidt"
> mailto:b...@kernel.crashing.org>> wrote:
>>
>> > >
>> > >> Outstanding Issues
>> > >> ==
>> > >> (1) Running DSCR register value inside a transaction does not
> seem to be saved
>> > >
There is an issue currently where NUMA information is used on powerpc
(and possibly ia64) before it has been read from the device-tree, which
leads to large slab consumption with CONFIG_SLUB and memoryless nodes.
NUMA powerpc non-boot CPU's cpu_to_node/cpu_to_mem is only accurate
after start_secon
In the presence of memoryless nodes, the workqueue code incorrectly uses
cpu_to_node() to determine what node to prefer memory allocations come
from. cpu_to_mem() should be used instead, which will use the nearest
NUMA node with memory.
Signed-off-by: Nishanth Aravamudan
diff --git a/kernel/work
[Apologies for the large Cc list, but I believe we have the following
interested parties:
x86 (recently posted memoryless node support)
ia64 (existing memoryless node support)
ppc (existing memoryless node support)
previous discussion of how to solve Anton's issue with slab usage
workqueue contrib
On Thu, 17 Jul 2014 11:36:07 +0200 Marek Szyprowski
wrote:
> MAX_CMA_AREAS is used by other subsystems (i.e. arch/arm/mm/dma-mapping.c),
> so we need to provide correct definition even if CMA is disabled.
> This patch fixes this issue.
>
> Reported-by: Sylwester Nawrocki
> Signed-off-by: Marek
On Thu, Jul 17, 2014 at 04:13:15PM +0200, Tomeu Vizoso wrote:
> In preparation to changing the clk provider API to use struct clk_core instead
> of struct clk.
Acked-by: Mark Brown
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Adds a way for clock consumers to set maximum and minimum rates. This can be
used for thermal drivers to set ceiling rates, or by misc. drivers to set
floor rates to assure a minimum performance level.
Signed-off-by: Tomeu Vizoso
---
drivers/clk/clk.c | 103
When a clock has multiple users, the WARNING on imbalance of
enable/disable may not show the guilty party since although they may
have commited the error earlier, the warning is emitted later when some
other user, presumably innocent, disables the clock.
Provide per-user clock enable/disable accou
In preparation to changing the clk provider API to use struct clk_core instead
of struct clk.
Signed-off-by: Tomeu Vizoso
---
sound/soc/mxs/mxs-saif.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c
index 231d7e7..a24367
To preserve git-bisectability, add aliases from the future provider API to the
existing public API.
Also includes clk-provider.h and clk-dev.h in a few places so the right
functions are defined.
Signed-off-by: Tomeu Vizoso
---
v4: * Add more clk-provider.h includes to clk implementations
Hi,
I'm retaking Rabin's patches [0] for splitting the clk API in two: one API for
clk consumers and another for providers. The consumer API uses a clk structure
that just keeps track of the consumer and has a reference to the actual
clk_core struct, which is used internally.
I have kept a patch
On 17.07.14 13:22, Mihai Caraman wrote:
Read guest last instruction from kvmppc_get_last_inst() allowing the function
to fail in order to emulate again. On bookehv architecture search for
the physical address and kmap it, instead of using Load External PID (lwepx)
instruction. This fixes an infi
On 17.07.14 13:22, Mihai Caraman wrote:
On book3e, guest last instruction is read on the exit path using load
external pid (lwepx) dedicated instruction. This load operation may fail
due to TLB eviction and execute-but-not-read entries.
This patch lay down the path for an alternative solution t
On 17.07.14 13:22, Mihai Caraman wrote:
In the context of replacing kvmppc_ld() function calls with a version of
kvmppc_get_last_inst() which allow to fail, Alex Graf suggested this:
"If we get EMULATE_AGAIN, we just have to make sure we go back into the guest.
No need to inject an ISI into th
In the rx irq handling part, we should clear the flags in RCSR not TCSR.
Signed-off-by: Nicolin Chen
---
sound/soc/fsl/fsl_sai.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index b10dbd8..1b6ee2c 100644
--- a/sound/soc/fsl
SAI will not clear their FIFOs after disabling TE/RE. Therfore, the driver
should take care the task so as not to let useless data remain in the FIFO.
Signed-off-by: Nicolin Chen
---
sound/soc/fsl/fsl_sai.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/sound/soc/fsl/
Nicolin Chen (2):
ASoC: fsl_sai: Reset FIFOs after disabling TE/RE
ASoC: fsl_sai: Fix incorrect register writing in fsl_sai_isr()
sound/soc/fsl/fsl_sai.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
--
1.8.4
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On Jul 17, 2014 9:11 PM, "Benjamin Herrenschmidt"
wrote:
>
> > >
> > >> Outstanding Issues
> > >> ==
> > >> (1) Running DSCR register value inside a transaction does not seem
to be saved
> > >> at thread.dscr when the process stops for ptrace examination.
> > >
> > > Hey Ben,
>
Hello Mark,
Am 17.07.2014 13:31, schrieb Mark Brown:
On Thu, Jul 17, 2014 at 11:11:45AM +0200, Heiko Schocher wrote:
Is it maybe the missing "support for the SPI subsystem's queue SPI messages"?
It shouldn't be that, that's still optional (sadly).
Thanks for this info! I digging in it ...
On ia64 and ppc64, the function pointer does not point the
entry address of the function, but the address of function
discriptor (which contains the entry address and misc
data.) Since the kprobes passes the function pointer stored
by NOKPROBE_SYMBOL() to kallsyms_lookup_size_offset() for
initalizi
(2014/07/17 20:17), Masami Hiramatsu wrote:
> (2014/07/17 18:38), Ingo Molnar wrote:
>>
>> * Masami Hiramatsu wrote:
>>
>>> Signed-off-by: Masami Hiramatsu
>>> Signed-off-by: Suzuki K. Poulose
>>
>> Looks good, but this is not a valid SOB sequence: if Suzuki wrote the
>> patch then he should be
On Thu, Jul 17, 2014 at 11:11:45AM +0200, Heiko Schocher wrote:
> Is it maybe the missing "support for the SPI subsystem's queue SPI messages"?
It shouldn't be that, that's still optional (sadly).
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On book3e, KVM uses load external pid (lwepx) dedicated instruction to read
guest last instruction on the exit path. lwepx exceptions (DTLB_MISS, DSI
and LRAT), generated by loading a guest address, needs to be handled by KVM.
These exceptions are generated in a substituted guest translation contex
In the context of replacing kvmppc_ld() function calls with a version of
kvmppc_get_last_inst() which allow to fail, Alex Graf suggested this:
"If we get EMULATE_AGAIN, we just have to make sure we go back into the guest.
No need to inject an ISI into the guest - it'll do that all by itself.
With
Add mising defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() for Book3E.
Signed-off-by: Mihai Caraman
---
v5-v2:
- no change
arch/powerpc/include/asm/mmu-book3e.h | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-book3e.h
b/arch/powerpc/inc
On book3e, guest last instruction is read on the exit path using load
external pid (lwepx) dedicated instruction. This load operation may fail
due to TLB eviction and execute-but-not-read entries.
This patch lay down the path for an alternative solution to read the guest
last instruction, by allow
The commit 1d628af7 "add load inst fixup" made an attempt to handle
failures generated by reading the guest current instruction. The fixup
code that was added works by chance hiding the real issue.
Load external pid (lwepx) instruction, used by KVM to read guest
instructions, is executed in a subs
Read guest last instruction from kvmppc_get_last_inst() allowing the function
to fail in order to emulate again. On bookehv architecture search for
the physical address and kmap it, instead of using Load External PID (lwepx)
instruction. This fixes an infinite loop caused by lwepx's data TLB miss
e
Signed-off-by: Michael Ellerman
---
tools/testing/selftests/powerpc/pmu/Makefile | 2 +-
tools/testing/selftests/powerpc/pmu/l3_bank_test.c | 48 ++
2 files changed, 49 insertions(+), 1 deletion(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/l3_bank_test.c
(2014/07/17 18:38), Ingo Molnar wrote:
>
> * Masami Hiramatsu wrote:
>
>> Signed-off-by: Masami Hiramatsu
>> Signed-off-by: Suzuki K. Poulose
>
> Looks good, but this is not a valid SOB sequence: if Suzuki wrote the
> patch then he should be the first SOB (and should have a From line as
> w
> >
> >> Outstanding Issues
> >> ==
> >> (1) Running DSCR register value inside a transaction does not seem to be
> >> saved
> >> at thread.dscr when the process stops for ptrace examination.
> >
> > Hey Ben,
> >
> > Any updates on this patch series ?
>
> Ben,
>
> Any updat
On 06/12/2014 02:39 PM, Anshuman Khandual wrote:
> On 05/23/2014 08:45 PM, Anshuman Khandual wrote:
>> This patch series adds five new ELF core note sections which can be
>> used with existing ptrace request PTRACE_GETREGSET/SETREGSET for accessing
>> various transactional memory and miscellan
On Wed, Jul 16, 2014 at 04:20:24PM -0600, Bjorn Helgaas wrote:
> > @@ -809,22 +799,23 @@ out_free:
> > }
> >
> > /**
> > - * pci_msi_check_device - check whether MSI may be enabled on a device
> > + * msi_check_device - check whether MSI may be enabled on a device
> > * @dev: pointer to the p
* Masami Hiramatsu wrote:
> (2014/07/16 22:28), Ingo Molnar wrote:
> >
> > * Masami Hiramatsu wrote:
> >
> >> (2014/07/15 16:16), Benjamin Herrenschmidt wrote:
> >>> On Tue, 2014-07-15 at 13:19 +1000, Michael Ellerman wrote:
> >>>
> > Signed-off-by: Masami Hiramatsu
> > Reported-by:
* Masami Hiramatsu wrote:
> Signed-off-by: Masami Hiramatsu
> Signed-off-by: Suzuki K. Poulose
Looks good, but this is not a valid SOB sequence: if Suzuki wrote the
patch then he should be the first SOB (and should have a From line as
well), if he acked it along the way then it should be an
MAX_CMA_AREAS is used by other subsystems (i.e. arch/arm/mm/dma-mapping.c),
so we need to provide correct definition even if CMA is disabled.
This patch fixes this issue.
Reported-by: Sylwester Nawrocki
Signed-off-by: Marek Szyprowski
---
include/linux/cma.h | 4
1 file changed, 4 insertio
Hello all,
I just tried a mpc83xx based board (similiar to the mpc8313erdb)
with linux v3.16-rc4 using the drivers/spi/spi-fsl-spi.c driver.
DT nodes for spi are the same as in arch/powerpc/boot/dts/mpc8313erdb.dts:
spi@7000 {
cell-index = <0>;
Hello,
On 2014-06-16 07:40, Joonsoo Kim wrote:
Currently, there are two users on CMA functionality, one is the DMA
subsystem and the other is the KVM on powerpc. They have their own code
to manage CMA reserved area even if they looks really similar.
>From my guess, it is caused by some needs on
On 17.07.14 05:19, Stewart Smith wrote:
The POWER8 processor has a Micro Partition Prefetch Engine, which is
a fancy way of saying "has way to store and load contents of L2 or
L2+MRU way of L3 cache". We initiate the storing of the log (list of
addresses) using the logmpp instruction and start r
On ia64 and ppc64, the function pointer does not point the
entry address of the function, but the address of function
discriptor (which contains the entry address and misc
data.) Since the kprobes passes the function pointer stored
by NOKPROBE_SYMBOL() to kallsyms_lookup_size_offset() for
initalizi
(2014/07/16 22:28), Ingo Molnar wrote:
>
> * Masami Hiramatsu wrote:
>
>> (2014/07/15 16:16), Benjamin Herrenschmidt wrote:
>>> On Tue, 2014-07-15 at 13:19 +1000, Michael Ellerman wrote:
>>>
> Signed-off-by: Masami Hiramatsu
> Reported-by: Tony Luck
> Tested-by: Tony Luck
> Cc
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