The current implementation of IOMMU on sPAPR does not use iommu_ops
and therefore does not call IOMMU API's bus_set_iommu() which
1) sets iommu_ops for a bus
2) registers a bus notifier
Instead, PCI devices are added to IOMMU groups from
subsys_initcall_sync(tce_iommu_init) which does basically the
Michael Ellerman wrote:
On Wed, 2013-12-11 at 11:30 +0100, Philippe Bergheaud wrote:
Benjamin Herrenschmidt wrote:
On Wed, 2013-12-11 at 17:29 +1100, Michael Ellerman wrote:
It would be nice if you could make an assertion about what the state of HMT
handling should be once your patch is a
Add PM support using callback function suspend and resume in
.driver.pm of spi_driver.
Signed-off-by: Hou Zhiqiang
---
v2:
- Replace .driver.suspend and .driver.resume with .driver.pm
- Use CONFIG_PM_SLEEP instead of CONFIG_PM
drivers/mtd/devices/m25p80.c | 37
Add PM support for eSPI controller using callback function suspend
and resume in .driver.pm of platform_driver.
Signed-off-by: Hou Zhiqiang
---
v2:
- Replace .driver.suspend and .driver.resume with .driver.pm
- Use CONFIG_PM_SLEEP instead of CONFIG_PM
- Add spi_master_suspend and spi_master_re
On Thu, Dec 12, 2013 at 12:18:56AM +, Geoff Levand wrote:
> Hi Eric,
>
> Here are a few minor fixes and improvements for kexec. Please consider.
FWIW,
Reviewed-by: Simon Horman
>
> -Geoff
>
> The following changes since commit 374b105797c3d4f29c685f3be535c35f5689b30e:
>
> Linux 3.13-
A couple more device tree properties that need byte swapping.
Signed-off-by: Anton Blanchard
---
arch/powerpc/kernel/crash_dump.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c
index 779a78c..11c1d06 1
The MSI code is miscalculating quotas in little endian mode.
Add required byteswaps to fix this.
Before we claimed a quota of 65536, after the patch we
see the correct value of 256.
Signed-off-by: Anton Blanchard
---
arch/powerpc/platforms/pseries/msi.c | 28 +++-
1 file
We need to byteswap ibm,pcie-link-speed-stats.
Signed-off-by: Anton Blanchard
---
arch/powerpc/platforms/pseries/pci.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/pci.c
b/arch/powerpc/platforms/pseries/pci.c
index 5f93856..70670a2 1
The NVRAM code has a number of endian issues. I noticed a very
confused error log count:
RTAS: 100663330 RTAS event begin
100663330 == 0x0622. 0x6 LE error logs and 0x22 BE error logs.
The pstore code has similar issues - if we write an oops in one
endian and attempt to rea
cpu_to_core_id() is missing a byteswap:
cat /sys/devices/system/cpu/cpu63/topology/core_id
201326592
Signed-off-by: Anton Blanchard
---
arch/powerpc/kernel/smp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 1
Some obvious issues:
cat /proc/ppc64/lparcfg
...
partition_id=16777216
...
partition_potential_processors=268435456
Signed-off-by: Anton Blanchard
---
arch/powerpc/platforms/pseries/lparcfg.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/platforms
During on LE boot we see:
Partition configured for 1073741824 cpus, operating system maximum is 2048.
Clearly missing a byteswap here.
Signed-off-by: Anton Blanchard
---
arch/powerpc/kernel/setup-common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/
From: Ulrich Weigand
There is a bug in using ptrace to access FPRs via PTRACE_PEEKUSR /
PTRACE_POKEUSR. In effect, trying to access any of the FPRs always
really accesses FPR0, which does seriously break debugging :-)
The problem seems to have been introduced by commit 3ad26e5c4459d
(Merge branc
Here are a number of little endian fixes found during testing of
2.6.13-*. Some of the interesting things:
A patch from Uli that fixes a nasty bug in PTRACE_PEEKUSR, basically
we always get FPR0 no matter which one we ask for.
Also included is a fix for the pseries NVRAM code, without it we
corru
On Wed, Dec 11, 2013 at 5:50 PM, Benjamin Herrenschmidt
wrote:
> On Wed, 2013-12-11 at 16:50 +0800, Liu ping fan wrote:
>> > why ? , All the hash routines do check for _PAGE_PRESENT via access
>> > variable.
>> >
>> Going through __hash_page_4K(4k on 4k HW), I do not find such check.
>> Am I wrong
Hello
On 12/12/2013 08:18 AM, Geoff Levand wrote:
> Add a new kexec preprocessor macro IND_FLAGS, which is the bitwise OR of
> all the possible kexec IND_ kimage_entry indirection flags.
>
> Having this macro allows for simplified code in the prosessing of the
> kexec kimage_entry items.
Where?
On Wed, 2013-12-11 at 11:30 +0100, Philippe Bergheaud wrote:
> Benjamin Herrenschmidt wrote:
> > On Wed, 2013-12-11 at 17:29 +1100, Michael Ellerman wrote:
> >
> >
> >>It would be nice if you could make an assertion about what the state of HMT
> >>handling should be once your patch is applied.
>
Add a new kexec preprocessor macro IND_FLAGS, which is the bitwise OR of
all the possible kexec IND_ kimage_entry indirection flags.
Having this macro allows for simplified code in the prosessing of the
kexec kimage_entry items.
Signed-off-by: Geoff Levand for Huawei, Linaro
---
include/linux/k
linux/kexec.h now defines an IND_FLAGS macro. Remove the local powerpc
definition and use the generic one.
Signed-off-by: Geoff Levand for Huawei, Linaro
---
arch/powerpc/kernel/machine_kexec_64.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/powerpc/kernel/machine_kexec_64.c
b/arc
Hi Eric,
Here are a few minor fixes and improvements for kexec. Please consider.
-Geoff
The following changes since commit 374b105797c3d4f29c685f3be535c35f5689b30e:
Linux 3.13-rc3 (2013-12-06 09:34:04 -0800)
are available in the git repository at:
git://git.linaro.org/people/geoff.levand
From: "Paul E. McKenney"
The powerpc lock acquisition sequence is as follows:
lwarx; cmpwi; bne; stwcx.; lwsync;
Lock release is as follows:
lwsync; stw;
If CPU 0 does a store (say, x=1) then a lock release, and CPU 1 does a
lock acquisition then a load (say, r1=y), then there
On Wed, Dec 11, 2013 at 04:11:51PM +0800, Hou Zhiqiang wrote:
> +#ifdef CONFIG_PM
> +static int of_fsl_espi_suspend(struct device *dev, pm_message_t state)
This should be CONFIG_PM_SLEEP. I'd also expect to see a call to
spi_master_suspend() here (and similarly for resume) - it won't do
anything
Add PM support using callback function suspend and resume in .driver of
spi_driver.
Signed-off-by: Hou Zhiqiang
---
drivers/mtd/devices/m25p80.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
Add PM support for eSPI controller using callback function suspend
and resume in .driver of platform_driver.
Signed-off-by: Hou Zhiqiang
---
drivers/spi/spi-fsl-espi.c | 57 ++
1 file changed, 57 insertions(+)
diff --git a/drivers/spi/spi-fsl-espi.c b
Signed-off-by: Shengzhou Liu
---
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/85xx/Kconfig
b/arch/powerpc/platforms/85xx/Kconfig
index 4d46349..e3
Add support for Freescale T2080/T2081 QDS Development System Board.
T2081QDS board shares the same PCB with T1040QDS with some differences.
The T2080QDS Development System is a high-performance computing,
evaluation, and development platform that supports T2080 QorIQ
Power Architecture processor,
There are much pci compatible with version on existing platforms.
To stop putting version numbers in device tree later, we add a
generic compatible 'fsl,qoriq-pcie'.
The version number is readable directly from a register.
Signed-off-by: Shengzhou Liu
---
arch/powerpc/sysdev/fsl_pci.c | 1 +
1 f
Add initial device tree for T2080/T2081 without DPAA components.
The T2080 SoC includes the following function and features:
- Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/6
Add elo3-dma-2.dtsi to support the third DMA controller.
This is used on T2080, T4240, etc.
MPIC registers for internal interrupts is non-continous in address, any
internal interrupt number greater than 159 should be added (16+208) to work,
adding 16 is due to external interrupts as usual, adding
Benjamin Herrenschmidt wrote:
On Wed, 2013-12-11 at 17:29 +1100, Michael Ellerman wrote:
It would be nice if you could make an assertion about what the state of HMT
handling should be once your patch is applied.
I think it's:
* The kernel should use HMT_MEDIUM_LOW as it's "default" priority
On Wed, 2013-12-11 at 16:50 +0800, Liu ping fan wrote:
> > why ? , All the hash routines do check for _PAGE_PRESENT via access
> > variable.
> >
> Going through __hash_page_4K(4k on 4k HW), I do not find such check.
> Am I wrong? Or I will send out a patch to fix that.
We pass a bitmask of flags t
On Wed, 2013-12-11 at 17:29 +1100, Michael Ellerman wrote:
> It would be nice if you could make an assertion about what the state of HMT
> handling should be once your patch is applied.
>
> I think it's:
>
> * The kernel should use HMT_MEDIUM_LOW as it's "default" priority
> * The kernel shoul
On Thu, Dec 5, 2013 at 6:53 PM, Aneesh Kumar K.V
wrote:
> Liu Ping Fan writes:
>
>> To enable the do_numa_page(), we should not fix _PAGE_NUMA in
>> hash_page(), so bail out for the case of pte_numa().
>>
>> Signed-off-by: Liu Ping Fan
>> ---
>> arch/powerpc/mm/hash_utils_64.c | 2 +-
>> 1 file
The period check of _PAGE_NUMA can probably happen on the correctly
placed page. For this case, when guest try to setup hpte in real mode,
we try to resolve the numa fault in real mode, since the switch between
guest context and host context costs too much.
Signed-off-by: Liu Ping Fan
---
arch/p
It will be helpful for next patch
Signed-off-by: Liu Ping Fan
---
Can it be merged with the next patch?
---
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
b/arch/powerpc/kvm/book3s_hv_rm_mmu.
To make _PAGE_NUMA take effect, we should force the checking when
guest uses hypercall to setup hpte.
Signed-off-by: Liu Ping Fan
---
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
b/arch/powerpc/kvm/bo
powerpc will use it in fast path.
Signed-off-by: Liu Ping Fan
---
include/linux/mm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 5ab0e22..420fb77 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -1092,6 +1092,8 @@ extern unsigned
This series is based on Aneesh's series "[PATCH -V2 0/5] powerpc: mm: Numa
faults support for ppc64"
For this series, I apply the same idea from the previous thread "[PATCH 0/3]
optimize for powerpc _PAGE_NUMA"
(for which, I still try to get a machine to show nums)
But for this series, I think
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