This patch adds conditional branch filtering support,
enabling it for PERF_SAMPLE_BRANCH_COND in perf branch
stack sampling framework by utilizing an available
software filter X86_BR_JCC.
Signed-off-by: Anshuman Khandual
Reviewed-by: Stephane Eranian
---
arch/x86/kernel/cpu/perf_event_intel_lbr
This patch adds enumeration for all available SW branch filters
in powerpc book3s code and also streamlines the look for the
SW branch filter entries while trying to figure out which all
branch filters can be supported in SW.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/core-book3s.c |
This patch adds some more raw event codes into the existing list
of event codes present in power7-events-list.h file. This tries
to complete the list of events supported in Power7 and matches
the raw event list with libpfm4 library.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/power7-e
This patch exports a set of POWER8 PMU raw event codes through
sysfs interface. Right now the raw event set matches the entire
set of POWER8 events found in libpfm4 library.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/power8-events-list.h | 146 +
arch/
This patchset adds some missing event list for POWER7 PMU raw
events which are exported through sysfs interface. Also adds a new
set of raw PMU events list for POWER8. I have completed some amount
of initial testing to verify the working of POWER8 raw event codes
through sysfs.
Before the
Le 15/10/2013 22:33, Scott Wood a écrit :
On Tue, 2013-10-15 at 18:27 +0200, leroy christophe wrote:
Le 11/10/2013 17:13, Joakim Tjernlund a écrit :
"Linuxppc-dev"
wrote on 2013/10/11 14:56:40:
Activating CONFIG_PIN_TLB allows access to the 24 first Mbytes of memory
at
bootup instead of 8.
On 10/14/2013 11:49 AM, Michael Ellerman wrote:
> On Fri, Oct 11, 2013 at 10:02:28AM +0530, Anshuman Khandual wrote:
>> On 10/11/2013 07:41 AM, Michael Ellerman wrote:
>>> On Thu, Oct 10, 2013 at 02:20:22PM +0530, Anshuman Khandual wrote:
>>>
Even I think this is not right. Instruction samplin
> > > > >
> > > > The device tree makes that quite clear.
> > >
> > > You chose to model it that way in the device tree; that doesn't make
> > > it clear that the hardware works that way or that it's a good way to
> > > model it.
> > >
> > > > Each PLL has several output which MUX node can take fro
On Power7, the DCACHE_SRC field in MMCRA register identifies the memory
hierarchy level (eg: L2, L3 etc) from which a data-cache miss for a
marked instruction was satisfied.
Use the 'perf_mem_data_src' object to export this hierarchy level to user
space. Some memory hierarchy levels in Power7 don'
On Power8, the LDST field in SIER identifies the memory hierarchy level
(eg: L1, L2 etc), from which a data-cache miss for a marked instruction
was satisfied.
Use the 'perf_mem_data_src' object to export this hierarchy level to user
space. Fortunately, the memory hierarchy levels in Power8 map fai
The perf event PM_MRK_GRP_CMPL is useful in analyzing memory hierarchy
of applications.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v6]:
- [Michael Ellerman]: Drop redundant PME_ prefix from event name.
arch/powerpc/perf/power8-events-list.h |1 +
1 file changed, 1 insertion(+)
perf_mem_data_src is an union that is initialized via the ->val field
and accessed via the bitmap fields. For this to work on big endian
platforms, we also need a big-endian represenation of perf_mem_data_src.
Cc: Stephane Eranian
Cc: Michael Ellerman
Signed-off-by: Sukadev Bhattiprolu
---
Chan
Export generic perf events for Power8 in sysfs.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v6]:
[Michael Ellerman] Drop PME_ prefix in macros
arch/powerpc/perf/power8-events-list.h | 20 +++
arch/powerpc/perf/power8-pmu.c | 44 +++---
We used the PME_ prefix earlier to avoid some macro/variable name
collisions. We have since changed the way we define/use the event
macros so we no longer need the prefix.
By dropping the prefix, we keep the the event macros consistent with
their official names.
Reported-by: Michael Ellerman
Si
The uninitialized variables cause warnings which are treated as errors
during build (without WERROR=0).
Signed-off-by: Sukadev Bhattiprolu
---
tools/perf/util/srcline.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/perf/util/srcline.c b/tools/perf/util/srcline.
Remove the local tools/perf/util/include/asm/byteorder.h and add
a few missing typedefs to tools/perf/util/include/linux/types.h.
The local byteorder.h complicates defining big/little endian versions
of data structures in include/uapi/linux/perf_event.h.
Fix proposed by Michael Ellerman.
Signed-
Implement instr_is_load_store_2_06() to detect whether a given instruction
is one of the fixed-point or floating-point load/store instructions in the
POWER Instruction Set Architecture v2.06.
This function will be used in a follow-on patch to save memory hierarchy
information of the load/store on
Power7 and Power8 processors save the memory hierarchy level (eg: L2, L3)
from which a load or store instruction was satisfied. Export this hierarchy
information to the user via the perf_mem_data_src object.
Thanks to input from Stephane Eranian, Michael Ellerman, Michael Neuling
and Anshuman Khan
The logic used in branch_opcode() to extract the opcode for an instruction
applies to non branch instructions also. So rename to instr_opcode().
Signed-off-by: Sukadev Bhattiprolu
---
arch/powerpc/lib/code-patching.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/ar
On 10/15/2013 09:38 PM, Mark Rutland wrote:
On Tue, Oct 08, 2013 at 04:22:07AM +0100, Hongbo Zhang wrote:
Hi Mark, Stephen and other DT maintainers?
The 1/3 had already been acked by Mark, and please have a further look
at this patch 2/3.
The DMA maintainer Vinod needs ack for the DT related p
On Wed, 18 Sep 2013 15:24:50 +0200, Thierry Reding
wrote:
> Interrupt references are currently resolved very early (when a device is
> created). This has the disadvantage that it will fail in cases where the
> interrupt parent hasn't been probed and no IRQ domain for it has been
> registered yet.
On Mon, 23 Sep 2013 10:13:38 +0200, Thierry Reding
wrote:
> On Sun, Sep 22, 2013 at 04:14:43PM -0500, Rob Herring wrote:
> > On Wed, Sep 18, 2013 at 8:24 AM, Thierry Reding
> > wrote:
> > > Instead of returning 0 for all errors, allow the precise error code to
> > > be propagated. This will be u
On Sun, 22 Sep 2013 16:19:27 -0500, Rob Herring wrote:
> On Wed, Sep 18, 2013 at 8:24 AM, Thierry Reding
> wrote:
> > The of_irq_to_resource() helper that is used to implement of_irq_count()
> > tries to resolve interrupts and in fact creates a mapping for resolved
> > interrupts. That's pretty h
On Sun, 22 Sep 2013 16:19:27 -0500, Rob Herring wrote:
> On Wed, Sep 18, 2013 at 8:24 AM, Thierry Reding
> wrote:
> > The of_irq_to_resource() helper that is used to implement of_irq_count()
> > tries to resolve interrupts and in fact creates a mapping for resolved
> > interrupts. That's pretty h
On Tue, 2013-10-15 at 17:36 +0200, Hendrik Brueckner wrote:
> Hi Benjamin,
>
> On Sat, Oct 12, 2013 at 07:43:24AM +1100, Benjamin Herrenschmidt wrote:
> > On Fri, 2013-10-11 at 14:47 +0200, Hendrik Brueckner wrote:
> > > The tiocmget/tiocmset callbacks are used to set and get modem status and
> >
On Tue, 2013-10-15 at 15:22 -0500, Scott Wood wrote:
> On Tue, 2013-10-15 at 14:53 -0500, Benjamin Herrenschmidt wrote:
> > On Tue, 2013-10-15 at 14:44 -0400, Martin Hicks wrote:
> > > On Tue, Oct 15, 2013 at 11:30 AM, Benjamin Herrenschmidt
> > > wrote:
> > > > On Tue, 2013-10-15 at 09:59 -0400,
On Tue, 2013-10-15 at 18:27 +0200, leroy christophe wrote:
> Le 11/10/2013 17:13, Joakim Tjernlund a écrit :
> > "Linuxppc-dev"
> >
> > wrote on 2013/10/11 14:56:40:
> >> Activating CONFIG_PIN_TLB allows access to the 24 first Mbytes of memory
> > at
> >> bootup instead of 8. It is needed for "big
On Tue, 2013-10-15 at 14:53 -0500, Benjamin Herrenschmidt wrote:
> On Tue, 2013-10-15 at 14:44 -0400, Martin Hicks wrote:
> > On Tue, Oct 15, 2013 at 11:30 AM, Benjamin Herrenschmidt
> > wrote:
> > > On Tue, 2013-10-15 at 09:59 -0400, Martin Hicks wrote:
> > >> I've tracked the start of the strang
On Tue, 2013-10-15 at 14:44 -0400, Martin Hicks wrote:
> On Tue, Oct 15, 2013 at 11:30 AM, Benjamin Herrenschmidt
> wrote:
> > On Tue, 2013-10-15 at 09:59 -0400, Martin Hicks wrote:
> >> I've tracked the start of the strange instruction pointers in 'perf
> >> report' to a commit by Anton:
> >>
> >
On Tue, Oct 15, 2013 at 11:30 AM, Benjamin Herrenschmidt
wrote:
> On Tue, 2013-10-15 at 09:59 -0400, Martin Hicks wrote:
>> I've tracked the start of the strange instruction pointers in 'perf
>> report' to a commit by Anton:
>>
>> commit 75382aa72f06823db7312ad069c3bae2eb3f8548
>> Author: Anton Bl
On Mon, 2013-10-14 at 20:59 -0500, Tang Yuantian-B29983 wrote:
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: 2013年10月15日 星期二 6:13
> > To: Tang Yuantian-B29983
> > Cc: Wood Scott-B07421; Mark Rutland; devicet...@vger.kernel.org;
> > linuxppc-dev@lists.ozlabs.org; Li Yang-Leo-R
leroy christophe wrote on 2013/10/15 18:27:00:
>
>
> Le 11/10/2013 17:13, Joakim Tjernlund a écrit :
> > "Linuxppc-dev"
> >
> > wrote on 2013/10/11 14:56:40:
> >> Activating CONFIG_PIN_TLB allows access to the 24 first Mbytes of
memory
> > at
> >> bootup instead of 8. It is needed for "big" ke
Le 11/10/2013 17:13, Joakim Tjernlund a écrit :
"Linuxppc-dev"
wrote on 2013/10/11 14:56:40:
Activating CONFIG_PIN_TLB allows access to the 24 first Mbytes of memory
at
bootup instead of 8. It is needed for "big" kernels for instance when
activating
CONFIG_LOCKDEP_SUPPORT. This needs to be
Hi Benjamin,
On Sat, Oct 12, 2013 at 07:43:24AM +1100, Benjamin Herrenschmidt wrote:
> On Fri, 2013-10-11 at 14:47 +0200, Hendrik Brueckner wrote:
> > The tiocmget/tiocmset callbacks are used to set and get modem status and
> > triggered through an tty ioctl.
> >
> > The dtr_rts() callback is dif
On Tue, 2013-10-15 at 09:59 -0400, Martin Hicks wrote:
> I've tracked the start of the strange instruction pointers in 'perf
> report' to a commit by Anton:
>
> commit 75382aa72f06823db7312ad069c3bae2eb3f8548
> Author: Anton Blanchard
> Date: Tue Jun 26 01:01:36 2012 +
>
> powerpc/perf
On Fri, Oct 11, 2013 at 04:29:39PM -0400, Mark Lord wrote:
> > static int xx_alloc_msix_irqs(struct xx_dev *dev, int nvec)
> > {
> > nvec = roundup_pow_of_two(nvec);/* assume 0 > nvec <= 16 */
> >
> > xx_disable_all_irqs(dev);
> >
> > pci_lock_msi(dev->pdev);
> >
> > rc =
> -Original Message-
> From: iommu-boun...@lists.linux-foundation.org [mailto:iommu-
> boun...@lists.linux-foundation.org] On Behalf Of Bjorn Helgaas
> Sent: Tuesday, October 15, 2013 5:46 AM
> To: Sethi Varun-B16395
> Cc: Yoder Stuart-B08248; linux-ker...@vger.kernel.org; iommu@lists.lin
I've tracked the start of the strange instruction pointers in 'perf
report' to a commit by Anton:
commit 75382aa72f06823db7312ad069c3bae2eb3f8548
Author: Anton Blanchard
Date: Tue Jun 26 01:01:36 2012 +
powerpc/perf: Move code to select SIAR or pt_regs into perf_read_regs
I don't know
On Tue, Oct 08, 2013 at 04:22:07AM +0100, Hongbo Zhang wrote:
> Hi Mark, Stephen and other DT maintainers?
>
> The 1/3 had already been acked by Mark, and please have a further look
> at this patch 2/3.
> The DMA maintainer Vinod needs ack for the DT related patches so that
> he can take all this
On Mon, Oct 14, 2013 at 13:09 -0700, Greg Kroah-Hartman wrote:
>
> On Mon, Oct 14, 2013 at 02:40:44PM -0500, Kumar Gala wrote:
> >
> > Greg,
> >
> > Wondering your thoughts on drivers/qe vs something like
> > drivers/soc/fsl/qe. The QuiccEngine (qe) is a communication core on
> > some of the Fr
From: Wang Dongsheng
Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.
Enable/Disable interface:
0, disable. 1, enable.
/sys/devices/system/cpu/cpuX/pw20_state
/sys/devices/system/cpu/cpuX/altivec_idle
Set wait time interface:(Nanosecond)
/sys/dev
From: Wang Dongsheng
Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.
From: Wang Dongsheng
Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.
Signed
From: Wang Dongsheng
E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
idle patches.
Signed-off-by: Wang Dongsheng
---
*v3:
Add bit definitions for PWRMGTCR0.
arch/powerpc/include/asm/reg.h | 2 ++
arch/powerpc/include/asm/reg_booke.h | 9 +
2 files changed, 1
Hi Alex,
Any update on this ?
-aneesh
"Aneesh Kumar K.V" writes:
> Hi All,
>
> This patch series support enabling HV and PR KVM together in the same kernel.
> We
> extend machine property with new property "kvm_type". A value of "HV" will
> force HV
> KVM and "PR" PR KVM. If we don't specif
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