On 06/02/2013 03:15 AM, gre...@linuxfoundation.org wrote:
>
> The patch below does not apply to the 3.9-stable tree.
> If someone wants it applied there, or to any other stable or longterm
> tree, then please email the backport, including the original git commit
> id to .
>
Please find the 3.9 b
On Mon, Jun 03, 2013 at 10:28:47AM +0800, Chen Yuanquan-B41889 wrote:
> On 06/01/2013 09:58 PM, Guenter Roeck wrote:
> >On Fri, May 31, 2013 at 03:44:07PM +1000, Benjamin Herrenschmidt wrote:
> >>On Thu, 2013-05-30 at 22:14 -0700, Guenter Roeck wrote:
> >>>On Wed, May 29, 2013 at 05:30:41PM +0800,
On 06/01/2013 09:58 PM, Guenter Roeck wrote:
On Fri, May 31, 2013 at 03:44:07PM +1000, Benjamin Herrenschmidt wrote:
On Thu, 2013-05-30 at 22:14 -0700, Guenter Roeck wrote:
On Wed, May 29, 2013 at 05:30:41PM +0800, Chen Yuanquan-B41889 wrote:
On 05/29/2013 01:35 AM, Guenter Roeck wrote:
bios_
On Sat, Jun 01, 2013 at 02:34:46PM +1000, Benjamin Herrenschmidt wrote:
>On Thu, 2013-05-30 at 16:24 +0800, Gavin Shan wrote:
>> The patch intends to add debugfs entry powerpc/EEH/PHBx so that
>> the administrator can inject EEH errors to specified PCI host
>> bridge for testing purpose.
>
>Use a b
On Sat, Jun 01, 2013 at 02:29:31PM +1000, Benjamin Herrenschmidt wrote:
>On Thu, 2013-05-30 at 16:24 +0800, Gavin Shan wrote:
>> The patch adds EEH backends for PowerNV platform. It's notable that
>> part of those EEH backends call to the I/O chip dependent backends.
>
>Add a check for my new OPALv
On Sat, Jun 01, 2013 at 02:24:30PM +1000, Benjamin Herrenschmidt wrote:
>On Thu, 2013-05-30 at 16:23 +0800, Gavin Shan wrote:
>> The patch adds the I/O chip backend to do PE reset. For now, we
>> focus on PCI bus dependent PE. If PHB PE has been put into error
>> state, the PHB will take complete r
On Sat, Jun 01, 2013 at 02:18:50PM +1000, Benjamin Herrenschmidt wrote:
>On Thu, 2013-05-30 at 16:23 +0800, Gavin Shan wrote:
>> The patch changes the criteria used to judge if the PE has been
>> resetted successfully. We needn't the PE status is exactly equal
>> to the combo: (EEH_STATE_MMIO_ACTIV
On Sat, Jun 01, 2013 at 02:14:24PM +1000, Benjamin Herrenschmidt wrote:
>On Thu, 2013-05-30 at 16:23 +0800, Gavin Shan wrote:
>> While processing EEH event interrupt from P7IOC, we need function
>> to retrieve the PE according to the indicated PCI host controller
>> (struct pci_controller). The pat
On Sat, Jun 01, 2013 at 02:13:03PM +1000, Benjamin Herrenschmidt wrote:
>On Thu, 2013-05-30 at 16:23 +0800, Gavin Shan wrote:
>> For EEH on PowerNV platform, the PCI devices will be probed to
>> check if they support EEH functionality. Different from the case
>> of EEH for pSeries platform, we will
Michael Ellerman wrote:
> On Thu, May 30, 2013 at 03:34:27PM +1000, Michael Neuling wrote:
> > On context switch, we should have no prefetch streams leak from one
> > userspace process to another. This frees up prefetch resources for the
> > next process.
> >
> > Based on patch from Milton Mill
Michael Ellerman writes:
> On Fri, May 31, 2013 at 04:33:24PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V"
>>
>> If a hash bucket gets full, we "evict" a more/less random entry from it.
>> When we do that we don't invalidate the TLB (hpte_remove) because we assume
>> the old trans
Benjamin Herrenschmidt writes:
> On Fri, 2013-05-31 at 14:45 +0530, Aneesh Kumar K.V wrote:
>
>> > The patch you are running on is what I'll send to Linus for 3.10 (+/-
>> > cosmetics). Aneesh second patch is a much larger rework which will be
>> > needed for THP but that will wait for 3.11. I'm
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