Hi all,
After merging the final tree, today's linux-next build (powerpc64
allnoconfig) failed like this:
In file included from arch/powerpc/include/asm/kvm_ppc.h:33:0,
from arch/powerpc/kernel/setup_64.c:67:
arch/powerpc/include/asm/kvm_book3s.h:65:20: error: field 'pte' has inco
Hello All:
summary:
the root cause is no enough room in exception area (0x5500 -- 0x7000).
it is caused by the patches "for saving/restre PPR":
they consumed much space of this area (0x5500 -- 0x7000).
for pseries_defconfig and ppc64_defconfig, it is still ok.
but for allmodconfig
On Wed, Mar 20, 2013 at 01:46:22PM -0600, Alex Williamson wrote:
>On Wed, 2013-03-20 at 20:31 +0100, Benjamin Herrenschmidt wrote:
>> On Wed, 2013-03-20 at 12:48 -0600, Alex Williamson wrote:
.../...
>> As for EEH, I will let Gavin describe in more details what he is doing,
>> though I wouldn't b
On Fri, 2013-03-15 at 15:26 +0800, Gavin Shan wrote:
> The config registers in [0, 0x40] is being supported by VFIO. Apart
> from that, the other config registers should be coverred by PCI or
> PCIe capability. However, there might have some PCI devices (be2net)
> who has config registers (0x7c) ou
> From: Ian Munsie
>
> This patch adds a new line to /proc/interrupts to account for the
> doorbell interrupts that each hardware thread has received. The total
> interrupt count in /proc/stat will now also include doorbells.
It's probably worth noting in the comment that these are not being
acc
This happens with threads that are offline due to CPU hotplug
(including threads that were never "plugged in" to begin with because
SMT is disabled).
Signed-off-by: Scott Wood
---
arch/powerpc/mm/mmu_context_nohash.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a
On 03/20/2013 01:45:03 AM, Wang Dongsheng-B40534 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, March 20, 2013 6:59 AM
> To: Wang Dongsheng-B40534
> Cc: Wood Scott-B07421; Gala Kumar-B11780;
linuxppc-dev@lists.ozlabs.org;
> Li Yang-R58472
> Subject: Re: [PAT
On 03/19/2013 10:48:53 PM, Wang Dongsheng-B40534 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, March 20, 2013 6:55 AM
> To: Wang Dongsheng-B40534
> Cc: Wood Scott-B07421; Gala Kumar-B11780;
linuxppc-dev@lists.ozlabs.org;
> Zhao Chenhui-B35336; Li Yang-R5847
On Wed, 2013-03-20 at 20:31 +0100, Benjamin Herrenschmidt wrote:
> On Wed, 2013-03-20 at 12:48 -0600, Alex Williamson wrote:
> > Perhaps my problem is that I don't have a clear picture of where
> > you're
> > going with this like I do for AER. For AER we're starting with
> > notification of an err
From: "Aneesh Kumar K.V"
We enable only if the we support 16MB page size.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable.h
b/arch/pow
From: "Aneesh Kumar K.V"
We now have pmd entries covering to 16MB range. To implement THP on powerpc,
we double the size of PMD. The second half is used to deposit the pgtable (PTE
page).
We also use the depoisted PTE page for tracking the HPTE information. The
information
include [ secondary g
From: "Aneesh Kumar K.V"
Hugepage invalidate involves invalidating multiple hpte entries.
Optimize the operation using H_BULK_REMOVE on lpar platforms.
On native, reduce the number of tlb flush.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/machdep.h|3 +
arch/powerpc/mm
From: "Aneesh Kumar K.V"
We now have pmd entries covering to 16MB range. To implement THP on powerpc,
we double the size of PMD. The second half is used to deposit the pgtable (PTE
page).
We also use the depoisted PTE page for tracking the HPTE information. The
information
include [ secondary g
From: "Aneesh Kumar K.V"
We could possibly avoid some of these changes because most of the HUGE PMD bits
map to PTE bits.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 31
arch/powerpc/kvm/book3s_64_mmu_hv.c | 12 -
arch/powerpc/kvm/bo
From: "Aneesh Kumar K.V"
HUGETLB clear the top bit of PMD entries and use that to indicate
a HUGETLB page directory. Since we store pfns in PMDs for THP,
we would have the top bit cleared by default. Add the top bit mask
for THP PMD entries and clear that when we are looking for pmd_pfn.
Signed-
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/perf/callchain.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/perf/callchain.c b/arch/powerpc/perf/callchain.c
index 578cac7..99262ce 100644
--- a/a
From: "Aneesh Kumar K.V"
handle large pages for get_user_pages_fast. Also take care of large page
splitting.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/gup.c | 84 +++--
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/
From: "Aneesh Kumar K.V"
For architectures like ppc64 we look at deposited pgtable when
calling pmdp_get_and_clear. So do the pgtable_trans_huge_withdraw
after finishing pmdp related operations.
Cc: Andrea Arcangeli
Signed-off-by: Aneesh Kumar K.V
---
mm/huge_memory.c |3 ++-
1 file chang
From: "Aneesh Kumar K.V"
THP code does PTE page allocation along with large page request and deposit them
for later use. This is to ensure that we won't have any failures when we split
hugepages to regular pages.
On powerpc we want to use the deposited PTE page for storing hash pte slot and
seco
From: "Aneesh Kumar K.V"
We look at both the segment base page size and actual page size and store
the pte-lp-encodings in an array per base page size.
We also update all relevant functions to take actual page size argument
so that we can use the correct PTE LP encoding in HPTE. This should also
From: "Aneesh Kumar K.V"
On archs like powerpc that support different hugepage sizes, HPAGE_SHIFT
and other derived values like HPAGE_PMD_ORDER are not constants. So move
that to hugepage_init
Cc: Andrea Arcangeli
Signed-off-by: Aneesh Kumar K.V
---
include/linux/huge_mm.h |3 ---
mm/huge
From: "Aneesh Kumar K.V"
This will be later used by powerpc THP support. In powerpc we want to use
pgtable for storing the hash index values. So instead of adding them to
mm_context list, we would like to store them in the second half of pmd
Cc: Andrea Arcangeli
Signed-off-by: Aneesh Kumar K.V
From: "Aneesh Kumar K.V"
We were not saving DAR and DSISR on MCE. Save then and also print the values
along with exception details in xmon.
Acked-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/exceptions-64s.S |9 +
arch/powerpc/xmon/xmon.c
From: "Aneesh Kumar K.V"
As per ISA doc, we encode base and actual page size in the LP bits of
PTE. The number of bit used to encode the page sizes depend on actual
page size. ISA doc lists this as
PTE LP actual page size
rrrz >=8KB
rrzz >=16KB
rzzz >=32K
From: "Aneesh Kumar K.V"
This make sure we handle multiple page size segment correctly.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_native_64.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/hash_native_64.c b/
From: "Aneesh Kumar K.V"
PAPR defines these errors as negative values. So print them accordingly
for easy debugging.
Acked-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/lpar.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/p
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h |3 ++-
arch/powerpc/mm/hash_utils_64.c | 12 +++-
arch/powerpc/mm/hugetlbpage-hash64.c |2 +-
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc
From: "Aneesh Kumar K.V"
This gives hint about different base and actual page size combination
supported by the platform.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_utils_64.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/mm/hash_ut
From: "Aneesh Kumar K.V"
In all these cases we are doing something similar to
HPTE_V_COMPARE(hpte_v, want_v) which ignores the HPTE_V_LARGE bit
With MPSS support we would need actual page size to set HPTE_V_LARGE
bit and that won't be available in most of these cases. Since we are ignoring
HPTE
From: "Aneesh Kumar K.V"
This make one PMD cover 16MB range. That helps in easier implementation of THP
on power. THP core code make use of one pmd entry to track the hugepage and
the range mapped by a single pmd entry should be equal to the hugepage size
supported by the hardware.
Acked-by: Pau
From: "Aneesh Kumar K.V"
This patch moves the common code to 32/64 bit headers and also duplicate
4K_PAGES and 64K_PAGES section. We will later change the 64 bit 64K_PAGES
version to support smaller PTE fragments. The patch doesn't introduce
any functional changes.
Acked-by: Paul Mackerras
Sign
From: "Aneesh Kumar K.V"
We allocate one page for the last level of linux page table. With THP and
large page size of 16MB, that would mean we are wasting large part
of that page. To map 16MB area, we only need a PTE space of 2K with 64K
page size. This patch reduce the space wastage by sharing t
From: "Aneesh Kumar K.V"
USE PTRS_PER_PTE to indicate the size of pte page. To support THP,
later patches will be changing PTRS_PER_PTE value.
Acked-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h |6 ++
arch/powerpc/mm/hash_low_64.S |
Hi,
This patchset adds transparent hugepage support for PPC64.
TODO:
* hash preload support in update_mmu_cache_pmd (we don't do that for hugetlb)
Some numbers:
The latency measurements code from Anton found at
http://ozlabs.org/~anton/junkcode/latency2001.c
THP disabled 64K page size
---
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 48f6d99..f472414 100644
--- a/arch/powerpc/kvm/book3s
On Wed, 2013-03-20 at 12:48 -0600, Alex Williamson wrote:
> Perhaps my problem is that I don't have a clear picture of where
> you're
> going with this like I do for AER. For AER we're starting with
> notification of an error, from that we build into how to retrieve the
> error information, and fi
On Wed, Mar 20, 2013 at 1:24 AM, Lucas Kannebley Tavares
wrote:
> This patch series first implements a function called pcie_get_speed_cap_mask
> in the PCI subsystem based off from drm_pcie_get_speed_cap_mask in drm. Then
> it removes the latter and fixes all references to it. And ultimately, it
>
On Tue, 2013-03-19 at 05:45 +0100, Benjamin Herrenschmidt wrote:
> On Mon, 2013-03-18 at 22:18 -0600, Alex Williamson wrote:
> > > Yes, EEH firmware call needn't going through VFIO. However, EEH has
> > > very close relationship with PCI and so VFIO-PCI does. Eventually, EEH
> > > has close relatio
EPCR.DUVD controls whether the debug events can come in
hypervisor mode or not. When KVM guest is using the debug
resource then we do not want debug events to be captured
in guest entry/exit path. So we set EPCR.DUVD when entering
and clears EPCR.DUVD when exiting from guest.
Debug instruction com
MPC5125 PSC controller has different registers than MPC5121.
This patch was originally created by Vladimir Ermakov
https://lists.ozlabs.org/pipermail/linuxppc-dev/2011-March/088954.html
Signed-off-by: Vladimir Ermakov
Signed-off-by: Matteo Facchinetti
---
arch/powerpc/include/asm/mpc52xx_psc.
Tested on MPC5125 Tower evaluation board with
mpc512x_defconfig compile configuration.
In detail, supports for:
- PSC / UART
- RTC
- ETH
- DIU
- I2C
Signed-off-by: Matteo Facchinetti
---
arch/powerpc/boot/dts/mpc5125twr.dts | 238 +
arch/powerpc/platforms/512x/
Add MPC5125 SoC in mpc512x family.
Inconvenient of MPC5125 SoC is to have differences in certain register
access between the others in the same family.
This patches add MPC5125 SoC unless adding configuration macro but
using general MPC512x kernel configuration.
Tested on Freescale MPC5125 tower
This provides a base for using 512x_generic platform on mpc5125 boards.
By this way 512x_GENERIC it could be used for all generic mpc512x boards
and kernel could be compiled with mpc512x_defconfig.
Signed-off-by: Matteo Facchinetti
---
arch/powerpc/configs/mpc512x_defconfig
On 03/20, Ananth N Mavinakayanahalli wrote:
>
> On Wed, Mar 20, 2013 at 01:43:01PM +0100, Oleg Nesterov wrote:
> > On 03/20, Oleg Nesterov wrote:
> > >
> > > But we did not install UPROBE_SWBP_INSN. Is it fine? I hope yes, just to
> > > verify. If not, we need 2 definitions. is_uprobe_insn() should
On 03/20, Ananth N Mavinakayanahalli wrote:
>
> On Wed, Mar 20, 2013 at 01:26:39PM +0100, Oleg Nesterov wrote:
> > But, at the same time, is the new definition fine for verify_opcode()?
> >
> > IOW, powerpc has another is_trap() insn(s) used by gdb, lets denote it X.
> > X != UPROBE_SWBP_INSN.
> >
On Wed, Mar 20, 2013 at 01:43:01PM +0100, Oleg Nesterov wrote:
> On 03/20, Oleg Nesterov wrote:
> >
> > But we did not install UPROBE_SWBP_INSN. Is it fine? I hope yes, just to
> > verify. If not, we need 2 definitions. is_uprobe_insn() should still check
> > insns == UPROBE_SWBP_INSN, and is_swbp_
On Wed, Mar 20, 2013 at 01:26:39PM +0100, Oleg Nesterov wrote:
> Hi Ananth,
>
> First of all, let me remind that I know nothing about powerpc ;)
>
> But iirc we already discussed this a bit, I forgot the details but
> still I have some concerns...
>
> On 03/20, Ananth N Mavinakayanahalli wrote:
On 03/20, Oleg Nesterov wrote:
>
> But we did not install UPROBE_SWBP_INSN. Is it fine? I hope yes, just to
> verify. If not, we need 2 definitions. is_uprobe_insn() should still check
> insns == UPROBE_SWBP_INSN, and is_swbp_insn() should check is_trap().
>
> And I am just curious, could you expla
Hi Ananth,
First of all, let me remind that I know nothing about powerpc ;)
But iirc we already discussed this a bit, I forgot the details but
still I have some concerns...
On 03/20, Ananth N Mavinakayanahalli wrote:
>
> GDB uses a variant of the trap instruction that is different from the
> one
Leekha Shaveta-B20052 would like to recall the message, "[PATCH 0/5]
powerpc/fsl-booke: Add B4(B4860QDS and B4420QDS) board support".
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Leekha Shaveta-B20052 wrote:
[SL] Kumar, Waiting for your response on it. Thought I have sent new
set of patches with the refactoring suggested, but not added PAMU in
them.
If you have the information, why wouldn't you include it in the patch?
The hard part has already been done for you!
--
EPCR.DUVD controls whether the debug events can come in
hypervisor mode or not. When KVM guest is using the debug
resource then we do not want debug events to be captured
in guest entry/exit path. So we set EPCR.DUVD when entering
and clears EPCR.DUVD when exiting from guest.
Debug instruction com
Any comments on this patch set??
Regards,
Sandeep
> -Original Message-
> From: Singh Sandeep-B37400
> Sent: Thursday, March 07, 2013 4:58 PM
> To: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org
> Cc: Singh Sandeep-B37400; Aggrwal Poonam-B10812
> Subject: [PATCH 1/4]
From: Ananth N Mavinakayanahalli
GDB uses a variant of the trap instruction that is different from the
one used by uprobes. Currently, running gdb on a program being traced
by uprobes causes an endless loop since uprobes doesn't understand
that the trap is inserted by some other entity and hence
-Original Message-
From: Leekha Shaveta-B20052
Sent: Tuesday, March 19, 2013 11:43 AM
To: 'Kumar Gala'
Cc: Timur Tabi; linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian
Minghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh
Ramneek-B31383; Sethi Varun-B16395
Subje
From: Shaveta Leekha
Signed-off-by: Vakul Garg
Signed-off-by: Shaveta Leekha
---
arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi | 118 +
1 files changed, 118 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi
diff --git a/ar
B4860 and B4420 are personalities of same silicon
* common silicon related features have been added in b4si-pre.dtsi and
b4si-post.dtsi
* the various silicon differences are in respective files of personalities
Enable a B4 SoC to boot. There are several things missing
from the device trees for
- Add support for B4 board's personalities in board file
b4_qds.c, It is common for B4 personalities B4860, B4420 and B4220QDS
- Add B4QDS support in Kconfig and Makefile
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architect
Signed-off-by: Shaveta Leekha
---
arch/powerpc/configs/corenet64_smp_defconfig |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig
b/arch/powerpc/configs/corenet64_smp_defconfig
index 36a5c41..abf21ea 100644
--- a/arch/powerpc/con
B4860QDS and B4420QDS share same QDS board
* common board features have been added in b4qds.dts
* various board differences are in respective files of personalities
Signed-off-by: Shaveta Leekha
Signed-off-by: Minghuan Lian
Signed-off-by: Andy Fleming
Signed-off-by: Poonam Aggrwal
Signed-off-
B4860 and B4420 are personalities of same silicon which share same QDS board.
B4420 is a reduced personality of b4860. To manage the common board and similar
silicon features, device tree refactoring is being done through this patch set.
* common board features have been added in b4qds.dts
* commo
From: Ian Munsie
This patch adds a new line to /proc/interrupts to account for the
doorbell interrupts that each hardware thread has received. The total
interrupt count in /proc/stat will now also include doorbells.
# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
16:
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