On Sat, 2013-03-16 at 09:34 +0800, Gavin Shan wrote:
> >Could you explain further how this will be used? How the device is
> >exposed to a guest is entirely a userspace construct, so why does vfio
> >need to know or care about this? I had assumed for AER that QEMU would
> >do the translation from
On Fri, 2013-03-15 at 13:41 -0600, Alex Williamson wrote:
>
> This basically gives userspace free access to any regions that aren't
> covered by known capabilities.
And ?
I mean seriously :-) We already had that discussion ... trying to
"protect" config space is just plain doomed. There is no p
On Fri, Mar 15, 2013 at 01:41:08PM -0600, Alex Williamson wrote:
>On Fri, 2013-03-15 at 15:26 +0800, Gavin Shan wrote:
>> The config registers in [0, 0x40] is being supported by VFIO. Apart
>> from that, the other config registers should be coverred by PCI or
>> PCIe capability. However, there migh
On Fri, Mar 15, 2013 at 01:29:00PM -0600, Alex Williamson wrote:
>On Fri, 2013-03-15 at 15:26 +0800, Gavin Shan wrote:
>> The address (domain/bus/slot/function) of the passed PCI device
>> looks quite different from perspective of host and guest. Some
>> architectures like PPC need to setup the map
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
> Signed-off-by: Shaveta Leekha
> ---
> arch/powerpc/boot/dts/b4420qds.dts | 168
> 1 files changed, 168 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/b4420qds.dts
If B4420 and B48
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
> Signed-off-by: Shaveta Leekha
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> Signed-off-by: Andy Fleming
> ---
> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 151 +++
> arch/powerpc/boot/dts/fsl/b4420si-pr
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
> Signed-off-by: Shaveta Leekha
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> Signed-off-by: Tang Yuantian
> Signed-off-by: Varun Sethi
> Signed-off-by: Minghuan Lian
> Signed-off-by: Ramneek Mehresh
> Signed-off-by: Kumar Gala
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
> Signed-off-by: Shaveta Leekha
> Signed-off-by: Minghuan Lian
> Signed-off-by: Andy Fleming
> Signed-off-by: Poonam Aggrwal
> Signed-off-by: Ramneek Mehresh
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc/boot/dts/b4860qds.dts | 178
On Fri, 2013-03-15 at 15:26 +0800, Gavin Shan wrote:
> The config registers in [0, 0x40] is being supported by VFIO. Apart
> from that, the other config registers should be coverred by PCI or
> PCIe capability. However, there might have some PCI devices (be2net)
> who has config registers (0x7c) ou
On Fri, 2013-03-15 at 15:26 +0800, Gavin Shan wrote:
> The address (domain/bus/slot/function) of the passed PCI device
> looks quite different from perspective of host and guest. Some
> architectures like PPC need to setup the mapping in host. The patch
> introduces additional VFIO device IOCTL com
On Thu, Mar 14, 2013 at 07:08:34PM +0100, Florian Fainelli wrote:
> + if (dev->err_interrupt == NO_IRQ) {
...
> + init_waitqueue_head(&dev->smi_busy_wait);
> +
> + dev->err_interrupt = platform_get_irq(pdev, 0);
> + if (dev->err_interrupt != -ENXIO) {
...
> + } else
> +
At the point of up_out label in kvmppc_hv_setup_htab_rma(),
srcu read lock is still held.
We have to release it before return.
Signed-off-by: Lai Jiangshan
Cc: Marcelo Tosatti
Cc: Gleb Natapov
Cc: Alexander Graf
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: k...@vger.kernel.org
Cc: kvm-
On 03/14/2013 09:47:58 PM, Jia Hongtao-B38951 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, March 14, 2013 12:38 AM
> To: David Laight
> Cc: Jia Hongtao-B38951; Wood Scott-B07421;
linuxppc-dev@lists.ozlabs.org;
> Stuart Yoder
> Subject: Re: [PATCH V4] powerpc
On Mar 15, 2013, at 1:14 AM, Jia Hongtao wrote:
> mpc85xx_pci_err_probe(struct platform_device *op) need platform_device
> declaration for definition. Otherwise, it will cause compile error if any
> files including fsl_pci.h without declaration of platform_device.
>
> Signed-off-by: Jia Hongtao
On Mar 14, 2013, at 10:14 AM, Paul Bolle wrote:
> The last user of Kconfig symbol 8260_PCI9 got removed in release v3.2.
> Remove this symbol too.
>
> Signed-off-by: Paul Bolle
> ---
> 0) Untested.
>
> 1) This probably is a second order effect of my commit
> 6805ab6daa2b589fe3242d05ddc47a9dbb0
On Mar 14, 2013, at 10:40 AM, Roy Zang wrote:
> E1000 NIC is a common used Ethernet card. Enable it as default
> for mpc85xx platform.
>
> other change is due to make savedefconfig
>
> Reported-by: Fu Jiwei
> Signed-off-by: Roy Zang
> ---
> tested on P1010rdb board
> arch/powerpc/configs/mpc8
On Mar 12, 2013, at 4:49 PM, Paul Bolle wrote:
> The Kconfig entry for QE_USB contains
> default y if USB_GADGET_FSL_QE
>
> But USB_GADGET_FSL_QE got removed in commit
> 193ab2a6070039e7ee2b9b9bebea754a7c52fd1b ("usb: gadget: allow multiple
> gadgets to be built"). This default will theref
Commit 193ab2a6070039e7ee2b9b9bebea754a7c52fd1b changed the USB gadget
Kconfig symbol from USB_GADGET_FSL_QE to USB_FSL_QE, but did not update
the associated symbol name in qe_lib to match.
Signed-off-by: Kumar Gala
---
arch/powerpc/sysdev/qe_lib/Kconfig |2 +-
1 file changed, 1 insertion(+)
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
> - Add support for B4 board's personalities in board file
> b4_qds.c, It is common for B4 personalities B4860 and B4420QDS
> - Add B4QDS support in Kconfig and Makefile
Code also references a B4220, what about it?
>
> B4860QDS is a high-perf
On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
> Signed-off-by: Shaveta Leekha
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> Signed-off-by: Tang Yuantian
> Signed-off-by: Varun Sethi
> Signed-off-by: Minghuan Lian
> Signed-off-by: Ramneek Mehresh
> Signed-off-by: Kumar Gala
On Mar 14, 2013, at 9:00 PM, Jia Hongtao-B38951 wrote:
>
>
>> -Original Message-
>> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
>> Sent: Friday, March 15, 2013 4:05 AM
>> To: Jia Hongtao-B38951
>> Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
>> mich...@ellerman.id.au; L
On Fri, Mar 15, 2013 at 2:55 AM, Shaveta Leekha wrote:
> + iommu@2 {
> + compatible = "fsl,pamu-v1.0", "fsl,pamu";
> + reg = <0x2 0x4000>;
> + interrupts = <
> + 24 2 0 0
> + 16 2 1 1>;
> +
Le 03/15/13 14:05, David Miller a écrit :
From: Florian Fainelli
Date: Fri, 15 Mar 2013 13:53:10 +0100
Le 03/15/13 13:55, David Miller a écrit :
From: David Miller
Date: Fri, 15 Mar 2013 08:53:21 -0400 (EDT)
From: Florian Fainelli
Date: Thu, 14 Mar 2013 19:08:31 +0100
This patch convert
From: Florian Fainelli
Date: Fri, 15 Mar 2013 13:53:10 +0100
> Le 03/15/13 13:55, David Miller a écrit :
>> From: David Miller
>> Date: Fri, 15 Mar 2013 08:53:21 -0400 (EDT)
>>
>>> From: Florian Fainelli
>>> Date: Thu, 14 Mar 2013 19:08:31 +0100
>>>
This patch converts the mv643xx_eth driv
Le 03/15/13 13:55, David Miller a écrit :
From: David Miller
Date: Fri, 15 Mar 2013 08:53:21 -0400 (EDT)
From: Florian Fainelli
Date: Thu, 14 Mar 2013 19:08:31 +0100
This patch converts the mv643xx_eth driver to use the mvmdio MDIO bus driver
instead of rolling its own implementation. As a
From: David Miller
Date: Fri, 15 Mar 2013 08:53:21 -0400 (EDT)
> From: Florian Fainelli
> Date: Thu, 14 Mar 2013 19:08:31 +0100
>
>> This patch converts the mv643xx_eth driver to use the mvmdio MDIO bus driver
>> instead of rolling its own implementation. As a result, all users of this
>> mv643
Le 03/15/13 13:53, David Miller a écrit :
From: Florian Fainelli
Date: Thu, 14 Mar 2013 19:08:31 +0100
This patch converts the mv643xx_eth driver to use the mvmdio MDIO bus driver
instead of rolling its own implementation. As a result, all users of this
mv643xx_eth driver are converted to regi
From: Florian Fainelli
Date: Thu, 14 Mar 2013 19:08:31 +0100
> This patch converts the mv643xx_eth driver to use the mvmdio MDIO bus driver
> instead of rolling its own implementation. As a result, all users of this
> mv643xx_eth driver are converted to register an "orion-mdio" platform_device.
>
Dear Florian Fainelli,
On Fri, 15 Mar 2013 12:07:12 +0100, Florian Fainelli wrote:
> Thanks to the help of Andrew Lunn, there is at least two known issues
> with this patch version:
>
> - we need to move up the mvmdio line in
> drivers/net/ethernet/marvell/Makefile to make sure that configs ha
Le 03/14/13 19:08, Florian Fainelli a écrit :
This patch converts the Marvell MV643XX ethernet driver to use the
Marvell Orion MDIO driver. As a result, PowerPC and ARM platforms
registering the Marvell MV643XX ethernet driver are also updated to
register a Marvell Orion MDIO driver. This driver
From: "Aneesh Kumar K.V"
This make one PMD cover 16MB range. That helps in easier implementation of THP
on power. THP core code make use of one pmd entry to track the hugepage and
the range mapped by a single pmd entry should be equal to the hugepage size
supported by the hardware.
Acked-by: Pau
From: "Aneesh Kumar K.V"
USE PTRS_PER_PTE to indicate the size of pte page. To support THP,
later patches will be changing PTRS_PER_PTE value.
Acked-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h |6 ++
arch/powerpc/mm/hash_low_64.S |
From: "Aneesh Kumar K.V"
Hugepage invalidate involves invalidating multiple hpte entries.
Optimize the operation using H_BULK_REMOVE on lpar platforms.
On native, reduce the number of tlb flush.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/machdep.h|3 +
arch/powerpc/mm
From: "Aneesh Kumar K.V"
We could possibly avoid some of these changes because most of the HUGE PMD bits
map to PTE bits.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 31
arch/powerpc/kvm/book3s_64_mmu_hv.c | 12 -
arch/powerpc/kvm/bo
From: "Aneesh Kumar K.V"
We were not saving DAR and DSISR on MCE. Save then and also print the values
along with exception details in xmon.
Acked-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/exceptions-64s.S |9 +
arch/powerpc/xmon/xmon.c
From: "Aneesh Kumar K.V"
In all these cases we are doing something similar to
HPTE_V_COMPARE(hpte_v, want_v) which ignores the HPTE_V_LARGE bit
With MPSS support we would need actual page size to set HPTE_V_LARGE
bit and that won't be available in most of these cases. Since we are ignoring
HPTE
From: "Aneesh Kumar K.V"
As per ISA doc, we encode base and actual page size in the LP bits of
PTE. The number of bit used to encode the page sizes depend on actual
page size. ISA doc lists this as
PTE LP actual page size
rrrz ≥8KB
rrzz ≥16KB
rzzz ≥32KB
r
From: "Aneesh Kumar K.V"
This patch moves the common code to 32/64 bit headers and also duplicate
4K_PAGES and 64K_PAGES section. We will later change the 64 bit 64K_PAGES
version to support smaller PTE fragments. The patch doesn't introduce
any functional changes.
Acked-by: Paul Mackerras
Sign
From: "Aneesh Kumar K.V"
THP code does PTE page allocation along with large page request and deposit them
for later use. This is to ensure that we won't have any failures when we split
hugepages to regular pages.
On powerpc we want to use the deposited PTE page for storing hash pte slot and
seco
From: "Aneesh Kumar K.V"
For architectures like ppc64 we look at deposited pgtable when
calling pmdp_get_and_clear. So do the pgtable_trans_huge_withdraw
after finishing pmdp related operations.
Cc: Andrea Arcangeli
Signed-off-by: Aneesh Kumar K.V
---
mm/huge_memory.c |3 ++-
1 file chang
From: "Aneesh Kumar K.V"
This gives hint about different base and actual page size combination
supported by the platform.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_utils_64.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/mm/hash_ut
From: "Aneesh Kumar K.V"
We now have pmd entries covering to 16MB range. To implement THP on powerpc,
we double the size of PMD. The second half is used to deposit the pgtable (PTE
page).
We also use the depoisted PTE page for tracking the HPTE information. The
information
include [ secondary g
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 48f6d99..f472414 100644
--- a/arch/powerpc/kvm/book3s
From: "Aneesh Kumar K.V"
We allocate one page for the last level of linux page table. With THP and
large page size of 16MB, that would mean we are wasting large part
of that page. To map 16MB area, we only need a PTE space of 2K with 64K
page size. This patch reduce the space wastage by sharing t
From: "Aneesh Kumar K.V"
HUGETLB clear the top bit of PMD entries and use that to indicate
a HUGETLB page directory. Since we store pfns in PMDs for THP,
we would have the top bit cleared by default. Add the top bit mask
for THP PMD entries and clear that when we are looking for pmd_pfn.
Signed-
From: "Aneesh Kumar K.V"
We now have pmd entries covering to 16MB range. To implement THP on powerpc,
we double the size of PMD. The second half is used to deposit the pgtable (PTE
page).
We also use the depoisted PTE page for tracking the HPTE information. The
information
include [ secondary g
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h |3 ++-
arch/powerpc/mm/hash_utils_64.c | 12 +++-
arch/powerpc/mm/hugetlbpage-hash64.c |2 +-
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc
From: "Aneesh Kumar K.V"
On archs like powerpc that support different hugepage sizes, HPAGE_SHIFT
and other derived values like HPAGE_PMD_ORDER are not constants. So move
that to hugepage_init
Cc: Andrea Arcangeli
Signed-off-by: Aneesh Kumar K.V
---
include/linux/huge_mm.h |3 ---
mm/huge
From: "Aneesh Kumar K.V"
PAPR defines these errors as negative values. So print them accordingly
for easy debugging.
Acked-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/lpar.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/p
From: "Aneesh Kumar K.V"
handle large pages for get_user_pages_fast. Also take care of large page
splitting.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/gup.c | 84 +++--
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/
From: "Aneesh Kumar K.V"
We enable only if the we support 16MB page size.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable.h
b/arch/pow
From: "Aneesh Kumar K.V"
This will be later used by powerpc THP support. In powerpc we want to use
pgtable for storing the hash index values. So instead of adding them to
mm_context list, we would like to store them in the second half of pmd
Cc: Andrea Arcangeli
Signed-off-by: Aneesh Kumar K.V
From: "Aneesh Kumar K.V"
We look at both the segment base page size and actual page size and store
the pte-lp-encodings in an array per base page size.
We also update all relevant functions to take actual page size argument
so that we can use the correct PTE LP encoding in HPTE. This should also
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/perf/callchain.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/perf/callchain.c b/arch/powerpc/perf/callchain.c
index 578cac7..99262ce 100644
--- a/a
Hi,
This patchset adds transparent hugepage support for PPC64.
TODO:
* powernv still doesn't boot
* hash preload support in update_mmu_cache_pmd
Some numbers:
The latency measurements code from Anton found at
http://ozlabs.org/~anton/junkcode/latency2001.c
THP disabled 64K page size
-
From: "Aneesh Kumar K.V"
This make sure we handle multiple page size segment correctly.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_native_64.c | 32 ++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/hash_native_64.c
Signed-off-by: Shaveta Leekha
---
arch/powerpc/configs/corenet64_smp_defconfig |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig
b/arch/powerpc/configs/corenet64_smp_defconfig
index 36a5c41..abf21ea 100644
--- a/arch/powerpc/con
Signed-off-by: Shaveta Leekha
---
arch/powerpc/boot/dts/b4420qds.dts | 168
1 files changed, 168 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/b4420qds.dts
diff --git a/arch/powerpc/boot/dts/b4420qds.dts
b/arch/powerpc/boot/dts/b44
Signed-off-by: Shaveta Leekha
Signed-off-by: Minghuan Lian
Signed-off-by: Andy Fleming
Signed-off-by: Poonam Aggrwal
Signed-off-by: Ramneek Mehresh
Signed-off-by: Kumar Gala
---
arch/powerpc/boot/dts/b4860qds.dts | 178
1 files changed, 178 insertions(+)
Signed-off-by: Shaveta Leekha
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
Signed-off-by: Andy Fleming
---
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 151 +++
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 70
2 files changed, 221 insertions(+),
- Add support for B4 board's personalities in board file
b4_qds.c, It is common for B4 personalities B4860 and B4420QDS
- Add B4QDS support in Kconfig and Makefile
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture pro
Signed-off-by: Shaveta Leekha
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
Signed-off-by: Tang Yuantian
Signed-off-by: Varun Sethi
Signed-off-by: Minghuan Lian
Signed-off-by: Ramneek Mehresh
Signed-off-by: Kumar Gala
Signed-off-by: Andy Fleming
---
arch/powerpc/boot/dts/fsl/b4860si-
Some architectures like PPC, especailly PowerNV platform, need to
do additional operations while adding or removing VFIO devices to
or from VFIO bus. The patch adds weak functions while to open,
release or ioctl for the specific VFIO device. Those functions could
be overrided by individual architec
The config registers in [0, 0x40] is being supported by VFIO. Apart
from that, the other config registers should be coverred by PCI or
PCIe capability. However, there might have some PCI devices (be2net)
who has config registers (0x7c) out of [0, 0x40], and don't have
corresponding PCI or PCIe capa
The address (domain/bus/slot/function) of the passed PCI device
looks quite different from perspective of host and guest. Some
architectures like PPC need to setup the mapping in host. The patch
introduces additional VFIO device IOCTL command to address that.
Signed-off-by: Gavin Shan
---
includ
The EEH (Enhanced Error Handling) is one of RAS features on IBM Power
machines. In order to support EEH, the VFIO needs some modification
as the patchset addresses. Firstly, the address (domain:bus:slot:function)
of passed PCI devices looks quite different from host and guest perspectives.
So we ha
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