As Michael Ellerman mentioned, arch/powerpc/sysdev/msi_bitmap.c
already implemented bitmap to manage (alloc/free) MSI interrupts.
The patch intends to use that mechanism to manage MSI interrupts
for PowerNV platform.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/pci-ioda.c | 1
于 2013/3/6 13:42, Michael Ellerman 写道:
On Wed, Mar 06, 2013 at 01:34:58PM +0800, Mike Qiu wrote:
于 2013/3/6 11:54, Michael Ellerman 写道:
On Tue, Mar 05, 2013 at 03:19:57PM +0800, Mike Qiu wrote:
于 2013/3/5 10:23, Michael Ellerman 写道:
On Tue, Jan 15, 2013 at 03:38:55PM +0800, Mike Qiu wrote:
d
On Wed, 6 Mar 2013 at 15:09, Michael Ellerman wrote:
> Thanks Christian. What hardware are you on?
This is a PowerBook G4, 32bit, uni-processor. Full dmesg, e.g.:
http://nerdbynature.de/bits/3.9.0-rc1/dmesg.txt
C.
--
BOFH excuse #88:
Boss' kid fucked up the machine
__
From: "Aneesh Kumar K.V"
This gives hint about different base and actual page size combination
supported by the platform.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_utils_64.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/mm/hash_ut
From: "Aneesh Kumar K.V"
handle large pages for get_user_pages_fast. Also take care of large page
splitting.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/gup.c | 84 +++--
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/
From: "Aneesh Kumar K.V"
This will be later used by powerpc THP support. In powerpc we want to use
pgtable for storing the hash index values. So instead of adding them to
mm_context list, we would like to store them in the second half of pmd
Cc: Andrea Arcangeli
Signed-off-by: Aneesh Kumar K.V
From: "Aneesh Kumar K.V"
Hugepage invalidate involves invalidating multiple hpte entries.
Optimize the operation using H_BULK_REMOVE on lpar platforms.
On native, reduce the number of tlb flush.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/machdep.h|3 +
arch/powerpc/mm
From: "Aneesh Kumar K.V"
We enable only if the we support 16MB page size.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable.h
b/arch/powe
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/perf/callchain.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/perf/callchain.c b/arch/powerpc/perf/callchain.c
index 578cac7..99262ce 100644
--- a/a
From: "Aneesh Kumar K.V"
Without this insert will return H_PARAMETER error. Also use
the signed variant when printing error.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hugepage-hash64.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/mm/hugepage-hash64.c
b/arch/
From: "Aneesh Kumar K.V"
We now have pmd entries covering to 16MB range. To implement THP on powerpc,
we double the size of PMD. The second half is used to deposit the pgtable (PTE
page).
We also use the depoisted PTE page for tracking the HPTE information. The
information
include [ secondary g
From: "Aneesh Kumar K.V"
HUGETLB clear the top bit of PMD entries and use that to indicate
a HUGETLB page directory. Since we store pfns in PMDs for THP,
we would have the top bit cleared by default. Add the top bit mask
for THP PMD entries and clear that when we are looking for pmd_pfn.
Signed-
From: "Aneesh Kumar K.V"
We now have pmd entries covering to 16MB range. To implement THP on powerpc,
we double the size of PMD. The second half is used to deposit the pgtable (PTE
page).
We also use the depoisted PTE page for tracking the HPTE information. The
information
include [ secondary g
From: "Aneesh Kumar K.V"
For architectures like ppc64 we look at deposited pgtable when
calling pmdp_get_and_clear. So do the pgtable_trans_huge_withdraw
after finishing pmdp related operations.
Cc: Andrea Arcangeli
Signed-off-by: Aneesh Kumar K.V
---
mm/huge_memory.c |3 ++-
1 file chang
From: "Aneesh Kumar K.V"
On archs like powerpc that support different huge page sizes, HPAGE_SHIFT
and other derived values like HPAGE_PMD_ORDER are not constants. So move
that to hugepage_init
Cc: Andrea Arcangeli
Signed-off-by: Aneesh Kumar K.V
---
include/linux/huge_mm.h |3 ---
mm/hug
From: "Aneesh Kumar K.V"
We allocate one page for the last level of linux page table. With THP and
large page size of 16MB, that would mean we are be wasting large part
of that page. To map 16MB area, we only need a PTE space of 2K with 64K
page size. This patch reduce the space wastage by sharin
From: "Aneesh Kumar K.V"
This make sure we handle multiple page size segment correctly.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_native_64.c | 52 +-
1 file changed, 40 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/mm/hash_nativ
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h |3 ++-
arch/powerpc/mm/hash_utils_64.c | 12 +++-
arch/powerpc/mm/hugetlbpage-hash64.c |2 +-
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 48f6d99..e50eb0d 100644
--- a/arch/powerpc/kvm/book3s_hv.
From: "Aneesh Kumar K.V"
This patch moves the common code to 32/64 bit headers and also duplicate
4K_PAGES and 64K_PAGES section. We will later change the 64 bit 64K_PAGES
version to support smaller PTE fragments. The patch doesn't introduce
any functional changes.
Acked-by: Paul Mackerras
Sign
From: "Aneesh Kumar K.V"
As per ISA doc, we encode base and actual page size in the LP bits of
PTE. The number of bit used to encode the page sizes depend on actual
page size. ISA doc lists this as
PTE LP actual page size
rrrz ≥8KB
rrzz ≥16KB
rzzz ≥32KB
r
From: "Aneesh Kumar K.V"
We look at both the segment base page size and actual page size and store
the pte-lp-encodings in an array per base page size.
We also update all relevant functions to take actual page size argument
so that we can use the correct PTE LP encoding in HPTE. This should also
From: "Aneesh Kumar K.V"
In all these cases we are doing something similar to
HPTE_V_COMPARE(hpte_v, want_v) which ignores the HPTE_V_LARGE bit
With MPSS support we would need actual page size to set HPTE_V_LARGE
bit and that won't be available in most of these cases. Since we are ignoring
HPTE
From: "Aneesh Kumar K.V"
With table_size as second argument, first argument of the function
is not the shift value, but rather index into the array. Rename the
variable to clarify the same.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc64.h |2 +-
arch/powerpc/mm/
From: "Aneesh Kumar K.V"
We will use this later with THP changes to request for pmd table of double the
size.
THP code does PTE page allocation along with large page request and deposit them
for later use. This is to ensure that we won't have any failures when we split
huge pages to regular page
From: "Aneesh Kumar K.V"
This make one PMD cover 16MB range. That helps in easier implementation of THP
on power. THP core code make use of one pmd entry to track the huge page and
the range mapped by a single pmd entry should be equal to the huge page size
supported by the hardware.
Acked-by: P
From: "Aneesh Kumar K.V"
USE PTRS_PER_PTE to indicate the size of pte page. To support THP,
later patches will be changing PTRS_PER_PTE value.
Acked-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h |6 ++
arch/powerpc/mm/hash_low_64.S |
From: "Aneesh Kumar K.V"
We were not saving DAR and DSISR on MCE. Save then and also print the values
along with exception details in xmon.
Acked-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/exceptions-64s.S |9 +
arch/powerpc/xmon/xmon.c
From: "Aneesh Kumar K.V"
PAPR defines these errors as negative values. So print them accordingly
for easy debugging.
Acked-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/lpar.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/p
Hi,
This patchset adds transparent huge page support for PPC64.
TODO:
* ppc64 KVM related changes
* powernv still doesn't boot
* hash preload support in update_mmu_cache_pmd
Some numbers:
The latency measurements code from Anton found at
http://ozlabs.org/~anton/junkcode/latency2001.c
THP dis
于 2013/3/6 11:54, Michael Ellerman 写道:
On Tue, Mar 05, 2013 at 03:19:57PM +0800, Mike Qiu wrote:
于 2013/3/5 10:23, Michael Ellerman 写道:
On Tue, Jan 15, 2013 at 03:38:55PM +0800, Mike Qiu wrote:
Adding a function irq_create_mapping_many() which can associate
multiple MSIs to a continous irq map
Hello Michael,
bisect tells me that since your commit 9422de3e953d0e60eb95f5430a9dd803eec1c6d7
"powerpc: Hardware breakpoints rewrite to handle non DABR breakpoint registers",
compiling linux fails with :
cc1: warnings being treated as errors
arch/powerpc/kernel/ptrace.c: In function 'arch_p
Michael Ellerman [mich...@ellerman.id.au] wrote:
| I suspect Arnaldo was either waiting for an ACK from Ben, or was
| expecting Ben to take it?
Arnaldo, here is an updated patch. If it is acked by Paul Mackerras,
Michael Ellerman or Ben, will you add it to your tree so the whole
patchset comes fro
On Wed, Mar 06, 2013 at 01:34:58PM +0800, Mike Qiu wrote:
> 于 2013/3/6 11:54, Michael Ellerman 写道:
> >On Tue, Mar 05, 2013 at 03:19:57PM +0800, Mike Qiu wrote:
> >>于 2013/3/5 10:23, Michael Ellerman 写道:
> >>>On Tue, Jan 15, 2013 at 03:38:55PM +0800, Mike Qiu wrote:
> diff --git a/kernel/irq/irq
Paul Mackerras writes:
> On Mon, Mar 04, 2013 at 04:28:42PM +0530, Aneesh Kumar K.V wrote:
>> The last one that ends up doing atomic_xor_bits which cause the mapcount
>> to go zero, will take the page off the list and free the page.
>
> No, look at the example again. page_table_free_rcu() won't
Paul Mackerras writes:
> On Mon, Mar 04, 2013 at 05:11:53PM +0530, Aneesh Kumar K.V wrote:
>> Paul Mackerras writes:
>> >> +static inline int hpte_actual_psize(struct hash_pte *hptep, int psize)
>> >> +{
>> >> + unsigned int mask;
>> >> + int i, penc, shift;
>> >> + /* Look at the 8 bit LP value
Paul Mackerras writes:
> On Mon, Mar 04, 2013 at 04:32:24PM +0530, Aneesh Kumar K.V wrote:
>>
>> Now with table_size argument, the first arg is no more the shift value,
>> rather it is index into the array. Hence i changed the variable name. I
>> will split that patch to make it easy for review.
On Wed, Mar 06, 2013 at 02:24:54PM +1100, Michael Ellerman wrote:
>On Tue, Mar 05, 2013 at 02:59:16PM +0800, Gavin Shan wrote:
>> The allocation of MSI is implemented based on bitmap and working
>> like the mechanism of strict round through the traced next available
>> cursor. However, the next ava
On Mon, Mar 04, 2013 at 05:23:14PM -0800, Christian Kujau wrote:
> On Tue, 26 Feb 2013 at 13:20, Tony Breeds wrote:
> > When building with CRYPTO_SHA1_PPC enabled we fail with:
> > ---
> > powerpc/crypto/sha1-powerpc-asm.S: Assembler messages:
> > powerpc/crypto/sha1-powerpc-asm.S:116: Error: can't
Paul Mackerras writes:
> On Mon, Mar 04, 2013 at 04:28:42PM +0530, Aneesh Kumar K.V wrote:
>> Paul Mackerras writes:
>>
>> > The other general comment I have is that it's not really clear when a
>> > page will be on the mm->context.pgtable_list and when it won't. I
>> > would like to see an in
Benjamin Herrenschmidt writes:
> On Mon, 2013-03-04 at 16:28 +0530, Aneesh Kumar K.V wrote:
>> I added the below comment when initializing the list.
>>
>> +#ifdef CONFIG_PPC_64K_PAGES
>> + /*
>> +* Used to support 4K PTE fragment. The pages are added to list,
>> +* when we
On Tue, Mar 05, 2013 at 03:19:57PM +0800, Mike Qiu wrote:
> 于 2013/3/5 10:23, Michael Ellerman 写道:
> >On Tue, Jan 15, 2013 at 03:38:55PM +0800, Mike Qiu wrote:
> >>Adding a function irq_create_mapping_many() which can associate
> >>multiple MSIs to a continous irq mapping.
> >>
> >>This is needed t
Setup the HFSCR (Hypervisor Facility Status and Control Register) for POWER8
when running HV=1. The HFSCR is the same as the FSCR except it's for
hypervisors. It controls the available of various facilities in OS and
userspace levels. It also indicates the cause of a hypervisor facility
unavaila
Add SPR number and bit definitions for the HFSCR (Hypervisor Facility Status
and Control Register).
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index
Benh,
This small series adds support for the HFSCR (Hypervisor Facility Status &
Control Register) in POWER8. It just sets the bits we know about at this
stage. This is useful only when MSR HV=1.
The HFSCR is the same as the FSCR except it's for hypervisors. It controls the
available of vario
On Tue, Mar 05, 2013 at 02:59:16PM +0800, Gavin Shan wrote:
> The allocation of MSI is implemented based on bitmap and working
> like the mechanism of strict round through the traced next available
> cursor. However, the next available MSI is never updated in current
> implementation. The patch fix
On 03/06/2013 07:15 AM, Kumar Gala wrote:
* Thread support on e6500
* Proper PAMU topology information
* DPAA related nodes (Qman, Bman, Fman, Rman, DCE)
* Prefetch Manager
* Thermal monitor unit
* Interlaken
Signed-off-by: Roy Zang
Signed-off-by: Minghuan Lian
Signed-off-by: Haiying Wang
Signed
Setup the HFSCR (Hypervisor Facility Status and Control Register) for POWER8
when running HV=1. The HFSCR is the same as the FSCR except but for
hypervisors.
This patch sets the facilities Linux knows about incase the firmware doesn't.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/cpu
Add SPR number and bit definitions for the HFSCR (Hypervisor Facility Status
and Control Register).
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index
Benh,
This small series adds support for the HFSCR (Hypervisor Facility Status &
Control Register) in POWER8. It just sets the bits we know about at this
stage. This is useful only when MSR HV=1.
Mikey
___
Linuxppc-dev mailing list
Linuxppc-dev@lists
On 03/05/2013 05:15:57 PM, Kumar Gala wrote:
Enable a baseline T4240 SoC to boot. There are several things missing
from the device trees for T4240:
* Thread support on e6500
Why did threads get removed from the device tree? It's supposed to
describe hardware, not what Linux currently suppo
* Add support for up to 24 cores on T4240 (includes threads)
* Enable AltiVec support (on T4240)
* Add T4240QDS board into build
* Other changes are due to general kernel update of defconfig
Signed-off-by: Kumar Gala
---
arch/powerpc/configs/corenet64_smp_defconfig |9 -
1 file chang
Some minor changes to the common corenet_ds.c code are needed to support
the T4240QDS:
* Add support for "fsl,qoriq-pcie-v3.0" controller
* Bump max # of IRQs to 512 (T4240 supports more interrupts than
previous SoCs).
Signed-off-by: Kumar Gala
---
arch/powerpc/platforms/85xx/Kconfig |
Signed-off-by: Minghuan Lian
Signed-off-by: Roy Zang
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Andy Fleming
Signed-off-by: Shaohui Xie
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Scott Wood
Signed-off-by: Kumar Gala
---
arch/powerpc/boot/dts/t4240qds.dts | 220
Enable a baseline T4240 SoC to boot. There are several things missing
from the device trees for T4240:
* Thread support on e6500
* Proper PAMU topology information
* DPAA related nodes (Qman, Bman, Fman, Rman, DCE)
* Prefetch Manager
* Thermal monitor unit
* Interlaken
Signed-off-by: Roy Zang
S
From: Vakul Garg
Add device tree for SEC (crypto engine) version 5.0 used on T4240.
Signed-off-by: Vakul Garg
Signed-off-by: Andy Fleming
Signed-off-by: Kumar Gala
---
arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi | 109 +
1 file changed, 109 insertions(+)
create mo
The e6500 core adds support for AltiVec on a Book-E class processor.
Connect up all the various exception handling code and build config
mechanisms to allow user spaces apps to utilize AltiVec.
Signed-off-by: Kumar Gala
---
arch/powerpc/include/asm/cputable.h |2 +-
arch/powerpc/includ
From: Roy ZANG
The T4240 utilizes a new PCIe controller block that has some minor
programming model differences from previous versions.
The major one that impacts initialization is how we determine the link
state. On the 3.x controllers we have a memory mapped SoC register
instead of a PCI conf
The e6500 core used on T4240 and B4860 SoCs from FSL implements MMUv2 of
the Power Book-E Architecture. However there are some minor differences
between it and other Book-E implementations.
Add support to parse SPRN_TLB1PS for the variable page sizes supported.
In the future this should be expand
From: Stuart Yoder
Signed-off-by: Stuart Yoder
---
-v2
-deo is EREF specific, changed name of property
arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi |1 +
arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi |1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/boot/dts/fs
From: Stuart Yoder
-also define a binding for fsl,eref-* properties
Signed-off-by: Stuart Yoder
---
-v3
-converted EREF specific properties to fsl,eref-*
.../devicetree/bindings/powerpc/fsl/cpus.txt | 21 +++
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi | 65 ++
On 03/05/2013 02:37:42 PM, Yoder Stuart-B08248 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, March 05, 2013 2:29 PM
> To: Yoder Stuart-B08248
> Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org; Yoder
Stuart-B08248
> Subject: Re: [PATCH][v2] powerpc
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, March 05, 2013 2:29 PM
> To: Yoder Stuart-B08248
> Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org; Yoder
> Stuart-B08248
> Subject: Re: [PATCH][v2] powerpc/e6500: Add Power ISA properties for e6500
> cores
>
On 03/05/2013 02:23:36 PM, Stuart Yoder wrote:
From: Stuart Yoder
Signed-off-by: Stuart Yoder
---
arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi |1 +
arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi |1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/e500mc
On 03/05/2013 02:16:42 PM, Stuart Yoder wrote:
From: Stuart Yoder
Signed-off-by: Stuart Yoder
---
-v2
-fix some typos
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi | 65
1 file changed, 65 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/e6500_pow
From: Stuart Yoder
Signed-off-by: Stuart Yoder
---
arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi |1 +
arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi |1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
b/arch/powerpc/boot/dts/fsl/e500
From: Stuart Yoder
Signed-off-by: Stuart Yoder
---
-v2
-fix some typos
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi | 65
1 file changed, 65 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/
On 03/05/2013 01:24:55 PM, Stuart Yoder wrote:
From: Stuart Yoder
Signed-off-by: Stuart Yoder
---
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi | 66
1 file changed, 66 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
diff --git
From: Stuart Yoder
Signed-off-by: Stuart Yoder
---
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi | 66
1 file changed, 66 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
b/
On 03/05/2013 04:12:30 AM, Jia Hongtao-B38951 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, March 05, 2013 7:46 AM
> To: Stuart Yoder
> Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Kumar Gala
> Subject: Re: [PATCH V4] powerpc/85xx: Add machine check ha
Hi Lai,
On 03/05/2013 09:55 PM, Lai Jiangshan wrote:
> Hi, Srivatsa,
>
> I'm sorry again, I delayed your works.
>
No, you didn't :-) I have been busy with some internal work lately,
so I haven't been able to go through the recent discussions and
review the new code carefully.. I'll get to it as
On 03/05/2013 09:11 PM, Lai Jiangshan wrote:
> On 03/03/13 01:11, Srivatsa S. Bhat wrote:
>> On 03/02/2013 06:44 PM, Lai Jiangshan wrote:
>>> From 345a7a75c314ff567be48983e0892bc69c4452e7 Mon Sep 17 00:00:00 2001
>>> From: Lai Jiangshan
>>> Date: Sat, 2 Mar 2013 20:33:14 +0800
>>> Subject: [PATCH]
On 03/05, Lai Jiangshan wrote:
>
> On 03/03/13 01:20, Oleg Nesterov wrote:
> > On 03/02, Lai Jiangshan wrote:
> >>
> >> +void lg_rwlock_local_read_unlock(struct lgrwlock *lgrw)
> >> +{
> >> + switch (__this_cpu_read(*lgrw->reader_refcnt)) {
> >> + case 1:
> >> + __this_cpu_write(*lgrw->r
On 03/05, Lai Jiangshan wrote:
>
> On 03/03/13 01:06, Oleg Nesterov wrote:
> > On 03/02, Michel Lespinasse wrote:
> >>
> >> My version would be slower if it needs to take the
> >> slow path in a reentrant way, but I'm not sure it matters either :)
> >
> > I'd say, this doesn't matter at all, simply
On Tue, Mar 5, 2013 at 7:54 AM, Lai Jiangshan wrote:
> On 03/03/13 01:06, Oleg Nesterov wrote:
>> On 03/02, Michel Lespinasse wrote:
>>>
>>> My version would be slower if it needs to take the
>>> slow path in a reentrant way, but I'm not sure it matters either :)
>>
>> I'd say, this doesn't matter
On 03/03/13 01:06, Oleg Nesterov wrote:
> On 03/02, Michel Lespinasse wrote:
>>
>> My version would be slower if it needs to take the
>> slow path in a reentrant way, but I'm not sure it matters either :)
>
> I'd say, this doesn't matter at all, simply because this can only happen
> if we race wit
On 02/03/13 03:47, Srivatsa S. Bhat wrote:
> On 03/01/2013 11:20 PM, Lai Jiangshan wrote:
>> On 28/02/13 05:19, Srivatsa S. Bhat wrote:
>>> On 02/27/2013 06:03 AM, Lai Jiangshan wrote:
On Wed, Feb 27, 2013 at 3:30 AM, Srivatsa S. Bhat
wrote:
> On 02/26/2013 09:55 PM, Lai Jiangshan wr
Hi Lai,
Just a few comments about your v2 proposal. Hopefully you'll catch
these before you send out v3 :)
- I would prefer reader_refcnt to be unsigned int instead of unsigned long
- I would like some comment to indicate that lgrwlocks don't have
reader-writer fairness and are thus somewhat di
From: Tudor Laurentiu
The ePAPR para-virtualization needs to happen very early
otherwise the bytechannel based console will silently
drop some of the early boot messages.
Before this patch, this is how the kernel log started:
-
> Brought up 2
From: Tudor Laurentiu
Critical interrupts are not handled on PPC64 BookE machines,
so when the first watchdog interrupt fires the machine will
freeze without a warning until it's rebooted by the second
watchdog trigger.
Plus, the interrupt isn't used anyway since the driver
expects a usermode app
On 03/03/13 01:11, Srivatsa S. Bhat wrote:
> On 03/02/2013 06:44 PM, Lai Jiangshan wrote:
>> From 345a7a75c314ff567be48983e0892bc69c4452e7 Mon Sep 17 00:00:00 2001
>> From: Lai Jiangshan
>> Date: Sat, 2 Mar 2013 20:33:14 +0800
>> Subject: [PATCH] lglock: add read-preference local-global rwlock
>>
On 03/03/13 01:20, Oleg Nesterov wrote:
> On 03/02, Lai Jiangshan wrote:
>>
>> +void lg_rwlock_local_read_unlock(struct lgrwlock *lgrw)
>> +{
>> +switch (__this_cpu_read(*lgrw->reader_refcnt)) {
>> +case 1:
>> +__this_cpu_write(*lgrw->reader_refcnt, 0);
>> +lg_local_
- Basic driver which does minimum intialization of the Le88266 SLIC device.
- The code was originally borrowed from Zarlink driver implementation.
- It is not full fledged SLIC driver code, it just does basic
initialization which is required to setup a voice data path between
channels. Thi
Freescale TDM controller consists of a TDM module supporting 128 channels
running at up to 50 Mbps with 8-bit and 16-bit word size. The TDM bus connects
gluelessly to most T1/E1 frames as well as to common buses such as the H.110,
SCAS, and MVIP. TDM also supports an I2S mode. The TDM module operat
TDM Framework is an attempt to provide a platform
independent layer which can offer a standard interface
for TDM access to different client modules. Beneath,
the framework layer can house different types of TDM
drivers to handle various TDM devices, the hardware
intricacies of the devices bei
tdm-summary.txt contains general description about TDM.
tdm-framework.txt contains specific description of TDM framework.
Signed-off-by: Sandeep Singh
Signed-off-by: Poonam Aggrwal
---
Documentation/tdm/tdm-framework.txt | 264 +++
Documentation/tdm/tdm-summar
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, March 05, 2013 7:46 AM
> To: Stuart Yoder
> Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Kumar Gala
> Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to fix
> PCIe erratum on mpc85xx
>
> On 03/04/20
> -Original Message-
> From: David Laight [mailto:david.lai...@aculab.com]
> Sent: Tuesday, March 05, 2013 1:16 AM
> To: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org;
> ga...@kernel.crashing.org
> Cc: Wood Scott-B07421
> Subject: RE: [PATCH V4] powerpc/85xx: Add machine check handler
On 03/05/2013 02:58 AM, Chen Gang wrote:
> 于 2013年02月28日 21:47, Jiri Slaby 写道:
when strlen(&pi->location_code[0]) == HVCS_CLC_LENGTH + 2
>> It cannot, pi->location_code is defined as char[HVCS_CLC_LENGTH + 1].
>>
>
> really, it is, I did not notice it.
>
> but I still prefer to modify
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