Hi Benjamin & Johannes,
Any thoughts about this patch?
> -Original Message-
> From: Wang Dongsheng-B40534
> Sent: Thursday, February 07, 2013 10:25 AM
> To: linuxppc-dev@lists.ozlabs.org
> Cc: Wood Scott-B07421; Li Yang-R58472; Zhao Chenhui-B35336; Wang
> Dongsheng-B40534
> Subject: [RFC]
On Thu, Feb 21, 2013 at 10:17:08PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> PAPR define these errors as negative values. So print them accordingly
^ defines
> for easy debugging.
>
> Signed-off-by: Aneesh Kumar K.V
Acked-by: Paul Mackerras
On Thu, Feb 21, 2013 at 10:17:13PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> We will use this later with THP changes. With THP we want to create PMD with
> twice the size. The second half will be used to depoist pgtable, which will
On Thu, Feb 21, 2013 at 10:17:11PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> This make one PMD cover 16MB range. That helps in easier implementation of THP
> on power. THP core code make use of one pmd entry to track the huge page and
> the range mapped by a single pmd entry s
On Thu, Feb 21, 2013 at 10:17:10PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> USE PTRS_PER_PTE to indicate the size of pte page.
>
> Signed-off-by: Aneesh Kumar K.V
> powerpc: Don't hard code the size of pte page
>
> USE PTRS_PER_PTE to indicate the size of pte page.
>
> Si
On Thu, Feb 21, 2013 at 10:17:09PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> We were not saving DAR and DSISR on MCE. Save then and also print the values
> along with exception details in xmon.
The one reservation I have about this is that xmon will now be
printing bogus valu
On Thu, Feb 21, 2013 at 10:17:12PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> We now have PTE page consuming only 2K of the 64K page.This is in order to
In fact the PTE page together with the hash table indexes occupies 4k,
doesn't it? The comments in the code are similarly c
On Thu, Feb 21, 2013 at 10:17:15PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> We look at both the segment base page size and actual page size and store
> the pte-lp-encodings in an array per base page size.
>
> Signed-off-by: Aneesh Kumar K.V
This needs more than 2 lines of
On Thu, Feb 21, 2013 at 10:17:14PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> Signed-off-by: Aneesh Kumar K.V
Needs a patch description. What is the motivation for doing this? Is
the new code completely equivalent to the old, or if not, what are the
differences? Etc.
Paul
David Gibson writes:
> On Thu, Feb 21, 2013 at 10:17:12PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V"
>>
>> We now have PTE page consuming only 2K of the 64K page.This is in order to
>> facilitate transparent huge page support, which works much better if our PMDs
>> cover 16MB in
None of the users of DEFINE_BITOP pass a postfix, and as far as I can
tell none ever did, so drop it.
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/bitops.h | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/bitops.h
b/arch/
On Thu, Feb 21, 2013 at 10:17:12PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> We now have PTE page consuming only 2K of the 64K page.This is in order to
> facilitate transparent huge page support, which works much better if our PMDs
> cover 16MB instead of 256MB.
>
> Inorder t
On Thu, 2013-02-21 at 23:06 +0100, Phileas Fogg wrote:
> Does it look like the new data at offset 0x80 and 0x88 in DT are MSR
> flags
> MSR_DR, MSR_IR and MSR_EE ?
Yes, that looks plausible though I would have expected ME to be set as
well ... Or it could be a CCR value. But it does look like som
On Thu, 2013-02-21 at 22:44 +0100, Phileas Fogg wrote:
> Stripped OpenWRT image:
>
>
> c001a474: 48 00 00 05 bl 0xc001a478
> c001a478: 7c a8 02 a6 mflrr5
> c001a47c: 38 a5 00 1c addir5,r5,28
> c
From: Michel Lespinasse
Subject: mm: use vm_unmapped_area() on powerpc architecture
Update the powerpc slice_get_unmapped_area function to make use of
vm_unmapped_area() instead of implementing a brute force search.
Signed-off-by: Michel Lespinasse
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
From: Michel Lespinasse
Subject: mm: remove free_area_cache use in powerpc architecture
As all other architectures have been converted to use vm_unmapped_area(),
we are about to retire the free_area_cache.
This change simply removes the use of that cache in
slice_get_unmapped_area(), which will
r Al stuff to go in first & fixup the conflict
> > before I send the pull request to Linus. I'm off travelling around but I
> > should be able to get stuff out this week-end.
>
> The merge looks fine to me. My TM signal tests still pass on
> next-20130221.
I think a
Benjamin Herrenschmidt wrote:
On Thu, 2013-02-21 at 21:38 +0100, Phileas Fogg wrote:
The new 8 bytes at offset 0x90 in dt.dump.hex look suspicously like
the kernel virtual address: 0xc001a4a0.
It does indeed. What does that address correspond to in the kernel
text ? Can you disassemble
Benjamin Herrenschmidt wrote:
On Thu, 2013-02-21 at 21:38 +0100, Phileas Fogg wrote:
The new 8 bytes at offset 0x90 in dt.dump.hex look suspicously like
the kernel virtual address: 0xc001a4a0.
It does indeed. What does that address correspond to in the kernel
text ? Can you disassemble
but I
> should be able to get stuff out this week-end.
The merge looks fine to me. My TM signal tests still pass on
next-20130221.
Thanks sfr!
Mikey
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On Thu, 2013-02-21 at 21:38 +0100, Phileas Fogg wrote:
> The new 8 bytes at offset 0x90 in dt.dump.hex look suspicously like
> the kernel virtual address: 0xc001a4a0.
It does indeed. What does that address correspond to in the kernel
text ? Can you disassemble around it with "objdump -D vm
Benjamin Herrenschmidt wrote:
On Wed, 2013-02-20 at 21:43 +0100, Phileas Fogg wrote:
I found the single commit which brakes kexec stuff for FreeBSD loader or other
custom ELF kernels on the PS3 console.
From 7230c5644188cd9e3fb380cc97dde00c464a3ba7 Mon Sep 17 00:00:00 2001
From: Benjamin He
This patch allows the use IRQ to notify the change of GPIO status on the MPC8xx
CPM IO ports. This then allows to associate IRQs to GPIOs in the Device Tree.
Ex:
CPM1_PIO_C: gpio-controller@960 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-c";
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_native_64.c|8
arch/powerpc/platforms/cell/beat_htab.c | 10 +-
arch/powerpc/platforms/ps3/htab.c |2 +-
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/ar
From: "Aneesh Kumar K.V"
handle large pages for get_user_pages_fast. Also take care of large page
splitting.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/gup.c | 84 +++--
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/
From: "Aneesh Kumar K.V"
Without this insert will return H_PARAMETER error. Also use
the signed variant when printing error.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/largepage-hash64.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/mm/largepage-hash64.c
b/arc
From: "Aneesh Kumar K.V"
We now have pmd entries covering to 16MB range. To implement THP on powerpc,
we double the size of PMD. The second half is used to deposit the pgtable (PTE
page).
We also use the depoisted PTE page for tracking the HPTE information. The
information
include [ secondary g
From: "Aneesh Kumar K.V"
HUGETLB clear the top bit of PMD entries and use that to indicate
a HUGETLB page directory. Since we store pfns in PMDs for THP,
we would have the top bit cleared by default. Add the top bit mask
for THP PMD entries and clear that when we are looking for pmd_pfn.
Signed-
From: "Aneesh Kumar K.V"
We enable only if the we support 16MB page size.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h | 33 +++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable.h
b/arch/p
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h |3 ++-
arch/powerpc/mm/hash_utils_64.c | 12 +++-
arch/powerpc/mm/hugetlbpage-hash64.c |2 +-
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc
Hi,
This patchset adds transparent huge page support for PPC64.
I am marking the series to linux-mm because the PPC64 implementation
required few interface changes to core THP code. I still have considerable
number of FIXME!! in the patchset mostly related to PPC64 mm susbsytem.
Those would requi
From: "Aneesh Kumar K.V"
We now have pmd entries covering to 16MB range. To implement THP on powerpc,
we double the size of PMD. The second half is used to deposit the pgtable (PTE
page).
We also use the depoisted PTE page for tracking the HPTE information. The
information
include [ secondary g
From: "Aneesh Kumar K.V"
On archs like powerpc that support different huge page sizes, HPAGE_SHIFT
and other derived values like HPAGE_PMD_ORDER are not constants. So move
that to hugepage_init
Signed-off-by: Aneesh Kumar K.V
---
include/linux/huge_mm.h |3 ---
mm/huge_memory.c|
From: "Aneesh Kumar K.V"
As per ISA doc, we encode base and actual page size in the LP bits of
PTE. The number of bit used to encode the page sizes depend on actual
page size. ISA doc lists this as
PTE LP actual page size
rrrz ≥8KB
rrzz ≥16KB
rzzz ≥32KB
r
From: "Aneesh Kumar K.V"
This will be later used by powerpc THP support. In powerpc we want to use
pgtable for storing the hash index values. So instead of adding them to
mm_context list, we would like to store them in the second half of pmd
Signed-off-by: Aneesh Kumar K.V
---
arch/s390/includ
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/s390/include/asm/pgtable.h |6 ++
arch/sparc/include/asm/pgtable_64.h |6 ++
include/asm-generic/pgtable.h |9 +
mm/huge_memory.c|7 ++-
4 files changed, 27 insert
From: "Aneesh Kumar K.V"
This gives hint about different base and actual page size combination
supported by the platform.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_utils_64.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/mm/hash_ut
From: "Aneesh Kumar K.V"
This make sure we handle Multiple page size segment correctly.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_native_64.c | 52 +-
1 file changed, 40 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/mm/hash_nativ
From: "Aneesh Kumar K.V"
We look at both the segment base page size and actual page size and store
the pte-lp-encodings in an array per base page size.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/machdep.h |3 +-
arch/powerpc/include/asm/mmu-hash64.h | 30 +---
From: "Aneesh Kumar K.V"
We now have PTE page consuming only 2K of the 64K page.This is in order to
facilitate transparent huge page support, which works much better if our PMDs
cover 16MB instead of 256MB.
Inorder to reduce the wastage, we now have multiple PTE page fragment
from the same PTE p
From: "Aneesh Kumar K.V"
We were not saving DAR and DSISR on MCE. Save then and also print the values
along with exception details in xmon.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/exceptions-64s.S |9 +
arch/powerpc/xmon/xmon.c |2 +-
2 files changed
From: "Aneesh Kumar K.V"
This make one PMD cover 16MB range. That helps in easier implementation of THP
on power. THP core code make use of one pmd entry to track the huge page and
the range mapped by a single pmd entry should be equal to the huge page size
supported by the hardware.
Signed-off-
From: "Aneesh Kumar K.V"
We will use this later with THP changes. With THP we want to create PMD with
twice the size. The second half will be used to depoist pgtable, which will
carry the hpte hash index value
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc64.h |7
From: "Aneesh Kumar K.V"
USE PTRS_PER_PTE to indicate the size of pte page.
Signed-off-by: Aneesh Kumar K.V
powerpc: Don't hard code the size of pte page
USE PTRS_PER_PTE to indicate the size of pte page.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h |6 ++
From: "Aneesh Kumar K.V"
PAPR define these errors as negative values. So print them accordingly
for easy debugging.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/lpar.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/pseries/lp
On 05.02.2013, at 05:10, Paul Mackerras wrote:
> The CFAR (Come-From Address Register) is a useful debugging aid that
> exists on POWER7 processors. Currently HV KVM doesn't save or restore
> the CFAR register for guest vcpus, making the CFAR of limited use in
> guests.
>
> This adds the necess
On Fri, Feb 15, 2013 at 03:18:35PM -0800, Doug Anderson wrote:
> There is simply no reason to be manually setting the private driver
> data to NULL in the remove/fail to probe cases. This is just extra
> cruft code that can be removed.
>
> A few notes:
> * Nothing relies on drvdata being set to N
There is a undesired behavior in the GIANFAR driver that causes a infinite loop
stalling the CPU when reception of PAUSE FRAMES.
I found this error during testing with a DSL modem (Westermo
http://www.westermo.com). This equipment spawns PAUSE FRAMES continuously on
its LAN side as long as the l
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