On 11/06/2012 07:23 AM, Michael Neuling wrote:
> + if (!found && pvr_version_is(PVR_POWER7)) {
> + /* check active counters for special buggy p7 overflow */
> + for (i = 0; i < cpuhw->n_events; ++i) {
> + event = cpuhw->event[i];
> +
If a PMC is about to overflow on a counter that's on an active perf event
(ie. less than 256 from the end) and a _different_ PMC overflows just at this
time (a PMC that's not on an active perf event), we currently mark the event as
found, but in reality it's not as it's likely the other PMC that ca
> Thanks for looking into this mess. One small thing we can fix in a
> follow up patch:
> > + if (!found)
> > + printk(KERN_WARNING "Can't find PMC that caused
>
> I think it would be worth making that a printk_ratelimited. We are
> probably dead at this stage but we shouldn't spam the
Hi,
Thanks for looking into this mess. One small thing we can fix in a
follow up patch:
> + if (!found)
> + printk(KERN_WARNING "Can't find PMC that caused
I think it would be worth making that a printk_ratelimited. We are
probably dead at this stage but we shouldn't spam the co
On POWER7 when we have really small counts left before overflow, we can take a
PMU IRQ, but the PMC gets wound back to just before the overflow.
If the kernel is setting the PMC to a value just before the overflow, we can
get interrupted again without the PMC making any progress (ie another buggy
If a PMC is about to overflow on a counter that's on an active perf event
(ie. less than 256 from the end) and a _different_ PMC overflows just at this
time (a PMC that's not on an active perf event), we currently mark the event as
found, but in reality it's not as it's likely the other PMC that ca
On 11/05/2012 05:19:20 AM, Varun Sethi wrote:
Added the following domain attributes required by FSL PAMU driver:
1. Subwindows field added to the iommu domain geometry attribute.
2. Added new iommu stash attribute, which allows setting of the
LIODN specific stash id parameter through IOMMU API
On 11/05/2012 05:04:13 PM, Timur Tabi wrote:
Varun Sethi wrote:
> + /* PAACE Offset 0x00 */
> + u32 wbah;/* only valid for
Primary PAACE */
> + u32 addr_bitfields; /* See P/S PAACE_AF_* */
> +
> + /* PAACE Offset 0x08 */
> + /* Interpretation of first 32 bits dependent on D
Varun Sethi wrote:
> Following is a brief description of the PAMU hardware:
> PAMU determines what action to take and whether to authorize the action on
> the basis of the memory address, a Logical IO Device Number (LIODN), and
> PAACT table (logically) indexed by LIODN and address. Hardware device
On 11/05/2012 04:10:46 PM, Timur Tabi wrote:
Varun Sethi wrote:
> Added the following domain attributes required by FSL PAMU driver:
> 1. Subwindows field added to the iommu domain geometry attribute.
> 2. Added new iommu stash attribute, which allows setting of the
>LIODN specific stash id p
Varun Sethi wrote:
> Added the following domain attributes required by FSL PAMU driver:
> 1. Subwindows field added to the iommu domain geometry attribute.
> 2. Added new iommu stash attribute, which allows setting of the
>LIODN specific stash id parameter through IOMMU API.
> 3. Added an attri
Varun Sethi wrote:
> This patchset provides the Freescale PAMU (Peripheral Access Management Unit)
> driver
> and the corresponding IOMMU API implementation. PAMU is the IOMMU present on
> Freescale
> QorIQ platforms. PAMU can authorize memory access, remap the memory address,
> and remap
> the
Jia Hongtao-B38951 wrote:
>>
>>> +#ifdef CONFIG_SUSPEND
>>> +static int fsl_pci_resume(struct platform_device *pdev)
>>> +{
>>> + struct pci_controller *hose;
>>> + struct resource pci_rsrc;
>>> +
>>> + hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
>>> + of_address_to_resource(pde
On Nov 4, 2012, at 9:23 PM, Jimi Xenidis wrote:
>
>
> On Nov 4, 2012, at 5:51 PM, Benjamin Herrenschmidt
> wrote:
>
>> On Sun, 2012-11-04 at 10:32 -0600, Jimi Xenidis wrote:
>>> I want to use the stuff in arch/platform/sysdev/dcr.c and I have a couple
>>> of questions:
>>> 1) anyone have a
Added the following domain attributes required by FSL PAMU driver:
1. Subwindows field added to the iommu domain geometry attribute.
2. Added new iommu stash attribute, which allows setting of the
LIODN specific stash id parameter through IOMMU API.
3. Added an attribute for enabling/disabling D
This patchset provides the Freescale PAMU (Peripheral Access Management Unit)
driver
and the corresponding IOMMU API implementation. PAMU is the IOMMU present on
Freescale
QorIQ platforms. PAMU can authorize memory access, remap the memory address,
and remap
the I/O transaction type.
This set
Add a new field in the device (powerpc) archdata structure for storing iommu
domain
information pointer. This pointer is stored when the device is attached to a
particular
domain.
Signed-off-by: Varun Sethi
---
arch/powerpc/include/asm/device.h |4
1 files changed, 4 insertions(+), 0
On powerpc, ptrace will disable hardware breakpoint request once the
breakpoint is hit. It is the responsibility of the caller to set it
again. However, when the caller sets the hardware breakpoint again
using ptrace(PTRACE_SET_DEBUGREG, child_pid, 0, addr), the hardware
breakpoint is not enabled.
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