[PATCH 6/6] powerpc: Implement PPR save/restore
When the task enters in to kernel space, the user defined priority (PPR)
will be saved in to PACA at the beginning of first level exception
vector and then copy from PACA to thread_info in second level vector.
PPR will be restored from thread_info be
[PATCH 5/6] powerpc: Macros for saving/restore PPR
Several macros are defined for saving and restore user defined PPR value.
Signed-off-by: Haren Myneni
---
arch/powerpc/include/asm/exception-64s.h | 29 +
arch/powerpc/include/asm/ppc_asm.h | 25 +++
[PATCH 4/6] powerpc: Define ppr in thread_struct
ppr in thread_struct is used to save PPR and restore it before process exits
from kernel.
This patch sets the default priority to 3 when tasks are created such
that users can use 4 for higher priority tasks.
Signed-off-by: Haren Myneni
---
arch/
[PATCH 3/6] powerpc: Increase exceptions arrays in paca struct to save PPR
Using paca to save user defined PPR value in the first level exception vector.
Signed-off-by: Haren Myneni
---
arch/powerpc/include/asm/exception-64s.h |1 +
arch/powerpc/include/asm/paca.h |6 +++---
2
[PATCH 2/6] powerpc: Define CPU_FTR_HAS_PPR
CPU_FTR_HAS_PPR is defined for POWER7.
Signed-off-by: Haren Myneni
---
arch/powerpc/include/asm/cputable.h |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cp
[PATCH 1/6] powerpc: Move branch instruction from ACCOUNT_CPU_USER_ENTRY to
caller
The first instruction in ACCOUNT_CPU_USER_ENTRY is 'beq' which checks for
exceptions coming from kernel mode. PPR value will be saved immediately after
ACCOUNT_CPU_USER_ENTRY and is also for user level exceptions.
[PATCH 0/6] powerpc: SMT priority (PPR) save and restore
On P7 systems, users can define SMT priority levels 2,3 and 4 for
processes so that some can run higher priority than the other ones.
In the current kernel, the default priority is set to 4 which prohibits
processes for using higher priority
Peter Zijlstra [pet...@infradead.org] wrote:
| On Tue, 2012-10-16 at 11:31 -0700, Sukadev Bhattiprolu wrote:
| > On a side note, how does the kernel on x86 use the 'config' information in
| > say /sys/bus/event_source/devices/cpu/format/cccr ? On Power7, the raw
| > code encodes the information su
Update ibm,architecture.vec for Sub-Processor Representation Level.
Allows us to support more than one parition per core.
This is untested so far as we don't have pHyp
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/prom_init.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/cputable.h | 12 ++--
arch/powerpc/include/asm/mmu.h |1 +
arch/powerpc/include/asm/reg.h |1 +
arch/powerpc/kernel/cputable.c | 21 +
4 files changed, 33 insertions(+), 2 deletions(
Just a copy of POWER7 for now. Will update with new code later.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/cpu_setup_power.S | 24
arch/powerpc/kernel/cputable.c|2 ++
2 files changed, 26 insertions(+)
diff --git a/arch/powerpc/kernel/cpu_setu
We are going to reuse this in POWER8 so make the name generic.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/Makefile |2 +-
.../{cpu_setup_power7.S => cpu_setup_power.S} |0
2 files changed, 1 insertion(+), 1 deletion(-)
rename arch/powerpc/kernel/{c
On Wed, Oct 31, 2012 at 01:09:56PM +1100, Michael Ellerman wrote:
> If we have two cache events that require different settings of the L2SEL
> bits in MMCR1 then we can not schedule those events simultaneously. Add
> logic to the constraint handling to express that.
>
> Signed-off-by: Michael Elle
If we have two cache events that require different settings of the L2SEL
bits in MMCR1 then we can not schedule those events simultaneously. Add
logic to the constraint handling to express that.
Signed-off-by: Michael Ellerman
---
arch/powerpc/perf/power7-pmu.c | 17 ++---
1 file c
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