From: Becky Bruce
Signed-off-by: Becky Bruce
---
arch/powerpc/configs/corenet64_smp_defconfig |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig
b/arch/powerpc/configs/corenet64_smp_defconfig
index 782822c..53741f4 100644
--- a
From: Becky Bruce
Updates from make savedefconfig.
Signed-off-by: Becky Bruce
---
arch/powerpc/configs/corenet64_smp_defconfig |5 -
1 files changed, 0 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig
b/arch/powerpc/configs/corenet64_smp_defconf
From: Becky Bruce
Signed-off-by: Becky Bruce
---
arch/powerpc/configs/corenet32_smp_defconfig |1 +
arch/powerpc/configs/mpc85xx_defconfig |1 +
arch/powerpc/configs/mpc85xx_smp_defconfig |1 +
3 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/confi
From: Becky Bruce
Results from updates via make savedefconfig.
Signed-off-by: Becky Bruce
---
arch/powerpc/configs/corenet32_smp_defconfig |8
arch/powerpc/configs/mpc85xx_defconfig |5 +
arch/powerpc/configs/mpc85xx_smp_defconfig |6 +-
3 files changed, 2
From: Becky Bruce
Allow hugetlb to be enabled on 64b FSL_BOOK3E. No platforms enable
it by default yet.
Signed-off-by: Becky Bruce
---
arch/powerpc/platforms/Kconfig.cputype |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/Kconfig.cputype
b/a
From: Becky Bruce
For 64-bit FSL_BOOKE implementations, gigantic pages need to be
reserved at boot time by the memblock code based on the command line.
This adds the call that handles the reservation, and fixes some code
comments.
It also removes the previous pr_err when reserve_hugetlb_gpages
i
From: Becky Bruce
Before hugetlb, at each level of the table, we test for
!0 to determine if we have a valid table entry. With hugetlb, this
compare becomes:
< 0 is a normal entry
0 is an invalid entry
> 0 is huge
This works because the hugepage code pulls the top bit of
From: Becky Bruce
I happened to comment this code while I was digging through it;
we might as well commit that. I also made some whitespace
changes - the existing code had a lot of unnecessary newlines
that I found annoying when I was working on my tiny laptop.
No functional changes.
Signed-of
From: Becky Bruce
The original 32-bit hugetlb implementation used PPC64 vs PPC32 to
determine which code path to take. However, the final hugetlb
implementation for 64-bit FSL ended up shared with the FSL
32-bit code so the actual check needs to be FSL_BOOK3E vs
everything else. This patch chan
From: Becky Bruce
This updates the hugetlb page table code to handle 64-bit FSL_BOOKE.
The previous 32-bit work counted on the inner levels of the page table
collapsing.
Signed-off-by: Becky Bruce
---
arch/powerpc/mm/hugetlbpage.c | 48 +++-
1 files change
From: Becky Bruce
This patch does 2 things: It corrects the code that determines the
size to write into MAS1 for the PPC_MM_SLICES case (this originally
came from David Gibson and I had incorrectly altered it), and it
changes the methodolody used to calculate the size for !PPC_MM_SLICES
to work f
From: Becky Bruce
There was an unconditional return of "1" in the original code
from David Gibson, and I dropped it because it wasn't needed
for FSL BOOKE 32-bit. However, not all systems (including 64-bit
FSL BOOKE) do loading of the hpte from the fault handler asm
and depend on this function r
From: Becky Bruce
If we don't have slices, we should be able to use the generic
hugetlb_get_unmapped_area() code
Signed-off-by: Becky Bruce
---
arch/powerpc/include/asm/page_64.h |2 ++
arch/powerpc/mm/hugetlbpage.c |6 ++
2 files changed, 4 insertions(+), 4 deletions(-)
diff
This series of patches contains mostly cleanup code that allows
the enablement of hugetlb for 64-bit Freescale BookE processors.
There are also some bits that I dropped from the 32-bit release
that are added back, as they are needed by other implementations.
Otherwise, it's mostly a bunch of code r
From: Thadeu Lima de Souza Cascardo
Date: Mon, 10 Oct 2011 13:46:54 -0300
> On Mon, Oct 10, 2011 at 01:42:23PM -0300, Thadeu Lima de Souza Cascardo wrote:
>> The doorbell register was being unconditionally swapped. In x86, that
>> meant it was being swapped to BE and written to the descriptor and
On Oct 10, 2011, at 9:45 AM, Joakim Tjernlund wrote:
That is an easy port but I will have to do that blind. Would you
mind take this for a spin on 2.4 first?
My current system is running 2.6, so I don't have much
interested in testing 2.4
The more interesting part is if one should use other
On 10/10/2011 04:56 AM, Suzuki K. Poulose wrote:
> #if defined(CONFIG_RELOCATABLE) && defined(CONFIG_44x)
> #define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) - PHYSICAL_START +
> (KERNELBASE + RELOC_OFFSET)))
> #define __pa(x) ((unsigned long)(x) + PHYSICAL_START - (KERNELBASE +
> RELOC_O
On 10/10/2011 12:17 PM, Suzuki Poulose wrote:
> On 10/10/11 20:45, Scott Wood wrote:
>> On 10/10/2011 04:55 AM, Suzuki K. Poulose wrote:
>>> The following patch implements the dynamic relocation processing for
>>> PPC32 kernel. relocate() accepts the target virtual address and
>>> relocates
>>> t
On 10/10/11 20:45, Scott Wood wrote:
On 10/10/2011 04:55 AM, Suzuki K. Poulose wrote:
The following patch implements the dynamic relocation processing for
PPC32 kernel. relocate() accepts the target virtual address and relocates
the kernel image to the same.
How much overhead is involved in
Dan Malek wrote on 2011/10/10 18:22:09:
>
>
> Hi Joakim.
>
> On Oct 10, 2011, at 4:38 AM, Joakim Tjernlund wrote:
>
> > This adds Large page support for 8xx and uses it
> > for all kernel RAM
>
> > - Dan, what do you think :)
>
> Since you asked, yes it looks great :-) Now, can we
> get this
On Mon, Oct 10, 2011 at 01:42:23PM -0300, Thadeu Lima de Souza Cascardo wrote:
> The doorbell register was being unconditionally swapped. In x86, that
> meant it was being swapped to BE and written to the descriptor and to
> memory, depending on the case of blue frame support or writing to
> doorbe
The doorbell register was being unconditionally swapped. In x86, that
meant it was being swapped to BE and written to the descriptor and to
memory, depending on the case of blue frame support or writing to
doorbell register. On PPC, this meant it was being swapped to LE and
then swapped back to BE
Hi Joakim.
On Oct 10, 2011, at 4:38 AM, Joakim Tjernlund wrote:
This adds Large page support for 8xx and uses it
for all kernel RAM
- Dan, what do you think :)
Since you asked, yes it looks great :-) Now, can we
get this into a more contemporary kernel? I'm
actually working on an 8x
Hi an,
On Mon, Oct 10, 2011 at 09:22:09AM -0700, Dan Malek wrote:
>
> Hi Joakim.
>
> On Oct 10, 2011, at 4:38 AM, Joakim Tjernlund wrote:
>
> >This adds Large page support for 8xx and uses it
> >for all kernel RAM
>
> >- Dan, what do you think :)
>
> Since you asked, yes it looks great :-
On 10/10/2011 04:55 AM, Suzuki K. Poulose wrote:
> The following patch implements the dynamic relocation processing for
> PPC32 kernel. relocate() accepts the target virtual address and relocates
> the kernel image to the same.
How much overhead is involved in a true relocatable kernel? Is it wo
Hi Joakim,
On Mon, Oct 10, 2011 at 01:30:06PM +0200, Joakim Tjernlund wrote:
> This is a backport from 2.6 which I did to overcome 8xx CPU
> bugs. 8xx does not update the DAR register when taking a TLB
> error caused by dcbX and icbi insns which makes it very
> tricky to use these insns. Also the
Use the new _PAGE_PSE to map all kernel RAM with 8 MB TLBs
Signed-off-by: Joakim Tjernlund
---
arch/ppc/mm/pgtable.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/mm/pgtable.c b/arch/ppc/mm/pgtable.c
index 866ae43..56e847e 100644
--- a/arch/ppc/mm/pgtable.c
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 22 +++---
1 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 8e3fe40..439e7f2 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kern
We need this bit for large pages(8MB). Adjust TLB code
to not clear bit 28 Mx_RPN
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S |8
include/asm-ppc/pgtable.h |6 +-
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/
This adds Large page support for 8xx and uses it
for all kernel RAM.
Further usage is possible, IMAP_ADDR and on board
flash comes to mind.
There is one bit free the pte which could be used for
selecting different large page sizes but that is for another
day.
- Dan, what do you think :)
Joakim
The new MMU/TLB code no longer sets ACCESSED unconditionally
so remove the exception.
Signed-off-by: Joakim Tjernlund
---
include/asm-ppc/pgtable.h | 10 --
1 files changed, 0 insertions(+), 10 deletions(-)
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index 6cfc5
Only update pte w.r.t ACCESSED if it isn't already set
Wrap ACCESSED with #ifndef NO_SWAP for too ease optimization.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/misc.S | 18 --
arch/ppc/lib/string.S | 17 -
2 files changed, 0 insertions(+), 35 deletions(-)
di
Use the PTE #defines where possible instead of
hardcoded constants.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 4bcd9b3..0f2101d 10
DTLB Error needs to adjust the HW PTE bits as DTLB Miss
does.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 402158d..4bcd9b3 100644
--- a/
8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S |8
include/asm-ppc/pgtable.h |5 +++--
2 files changed,
only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/pp
branch to common code in DTLB Miss instead.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 23 ++-
1 files changed, 2 insertions(+), 21 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 0891b96..367fec0 100644
--- a/a
Update the TLB asm to make proper use of _PAGE_DIRTY and _PAGE_ACCESSED.
Get rid of _PAGE_HWWRITE too.
Pros:
- PRESENT is copied to ACCESSED, fixing accounting
- DIRTY is mapped to 0x100, the changed bit, and is set directly
when a page has been made dirty.
- Proper RO/RW mapping of user
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 149 +
The wrong register was loaded into MD_RPN.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index b3aff21..9d8a1b5 100644
--- a/arch/ppc/kernel/head_8
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 84 +++
1 files changed, 22 insertions(+), 62 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index f9a30f3..ba05a57 100644
--- a/arch/ppc/kernel/head_8xx
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separately as 8xx MMU don't.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/kernel
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
This also fixes MachineCheck to pass DAR and DSISR as well.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 18 +
This is a backport from 2.6 which I did to overcome 8xx CPU
bugs. 8xx does not update the DAR register when taking a TLB
error caused by dcbX and icbi insns which makes it very
tricky to use these insns. Also the dcbst wrongly sets the
the store bit when faulting into DTLB error.
A few more bugs ve
On Mon, 2011-10-10 at 11:29 +0200, Eli Cohen wrote:
> On Mon, Oct 10, 2011 at 11:24:05AM +0200, Benjamin Herrenschmidt wrote:
> > On Mon, 2011-10-10 at 11:16 +0200, Eli Cohen wrote:
> >
> > > Until then I think we need to have the logic working right on ppc and
> > > measure if blue flame buys us
Now that we have relocatable kernel, supporting CRASH_DUMP only requires
turning the switches on for UP machines.
We don't have kexec support on 47x yet. Enabling SMP support would be done
as part of enabling the PPC_47x support.
Signed-off-by: Suzuki K. Poulose
Cc: Josh Boyer
Cc: Benj
The following patch adds relocatable support for PPC44x kernel.
We find the runtime address of _stext and relocate ourselves based
on the following calculation.
virtual_base = ALIGN(KERNELBASE,256M) +
MODULO(_stext.run,256M)
relocate() is called with the Effective
The following patch implements the dynamic relocation processing for
PPC32 kernel. relocate() accepts the target virtual address and relocates
the kernel image to the same.
Currently the following relocation types are handled :
R_PPC_RELATIVE
R_PPC_ADDR16_LO
R_PPC_ADDR16_
The following series implements CRASH_DUMP support for PPC440x. The
patches apply on top of power-next tree. This set also adds support
for CONFIG_RELOCATABLE on 44x.
I have tested the patches on Ebony and Virtex(QEMU Emulated). Testing
these patches would require latest snapshot of kexec-tools gi
On Mon, Oct 10, 2011 at 11:24:05AM +0200, Benjamin Herrenschmidt wrote:
> On Mon, 2011-10-10 at 11:16 +0200, Eli Cohen wrote:
>
> > Until then I think we need to have the logic working right on ppc and
> > measure if blue flame buys us any improvement in ppc. If that's not
> > the case (e.g becaus
On Mon, 2011-10-10 at 11:16 +0200, Eli Cohen wrote:
> Until then I think we need to have the logic working right on ppc and
> measure if blue flame buys us any improvement in ppc. If that's not
> the case (e.g because write combining is not working), then maybe we
> should avoid using blueflame in
On Mon, Oct 10, 2011 at 11:01:24AM +0200, Benjamin Herrenschmidt wrote:
>
> The case where things get a bit more nasty is when you try to use MMIO
> for low latency small-data type transfers instead of DMA, in which case
> you do want the ability for the chipset to write-combine and control the
>
On Mon, 2011-10-10 at 10:47 +0200, Eli Cohen wrote:
> On Mon, Oct 10, 2011 at 09:40:17AM +0100, David Laight wrote:
> >
> > Actually memory barriers shouldn't really be added to
> > any of these 'accessor' functions.
> > (Or, at least, ones without barriers should be provided.)
> >
> > The driver
On Mon, 2011-10-10 at 09:40 +0100, David Laight wrote:
> > What is this __iowrite64_copy... oh I see
> >
> > Nice, somebody _AGAIN_ added a bunch of "generic" IO
> > accessors that are utterly wrong on all archs except
> > x86 (ok, -almost-).
> > There isn't a single bloody memory barrier in ther
On Mon, Oct 10, 2011 at 09:40:17AM +0100, David Laight wrote:
>
> Actually memory barriers shouldn't really be added to
> any of these 'accessor' functions.
> (Or, at least, ones without barriers should be provided.)
>
> The driver may want to to a series of writes, then a
> single barrier, befor
> What is this __iowrite64_copy... oh I see
>
> Nice, somebody _AGAIN_ added a bunch of "generic" IO
> accessors that are utterly wrong on all archs except
> x86 (ok, -almost-).
> There isn't a single bloody memory barrier in there !
Actually memory barriers shouldn't really be added to
any of
On Mon, 2011-10-10 at 09:20 +0100, David Laight wrote:
>
> For the above I'd actually suggest making 'doorbell_qpn' have the
> correct endianness in order to avoid the (potential) swap every
> time it is set.
Well, the problem is that either you'll end up swapping on x86 or you'll
end up swapping
> Then, this statement:
>
> *(u32 *) (&tx_desc->ctrl.vlan_tag) |= ring->doorbell_qpn;
...
> instead do ... :
> *(u32 *) (&tx_desc->ctrl.vlan_tag) |=
cpu_to_be32(ring->doorbell_qpn);
>
> (Also get rid of that cast and define vlan_tag as a __be32 to start
> with).
Agreed, casts that chan
On Sun, 2011-10-09 at 12:30 +0200, Eli Cohen wrote:
> > Ideally you want to avoid that swapping altogether and use the right
> > accessor that indicates that your register is BE to start with. IE.
> > remove the swab32 completely and then use something like
> > iowrite32be() instead of writel().
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