Re: [RFC PATCH 1/2] RapidIO: Add DMA Engine support for RIO data transfers

2011-10-05 Thread Williams, Dan J
On Mon, Oct 3, 2011 at 9:52 AM, Bounine, Alexandre wrote: > Vinod Koul wrote: >> >> On Fri, 2011-09-30 at 17:38 -0400, Alexandre Bounine wrote: >> Please CC *maintainers* on your patches, get_maintainers.pl will tell >> you who. Adding Dan here > > Based on https://lkml.org/lkml/2011/2/14/67 and u

Re: Enabling MBX in MPC5121

2011-10-05 Thread Tabi Timur-B04825
2011/9/30 Einar Már Björgvinsson : > Hi all > > I am interested in enabling the GPU on the MPC5121 for 2d/3d acceleration. > I've read some misleading informations about the status of support in Linux > for this. > What is the status today ? is it easily possible ? if so, how ? There may be some s

[PATCH] hvc_console: display printk messages on console.

2011-10-05 Thread Miche Baker-Harvey
printk only works for "registered consoles." Currently, the hvc_console code calls register_console() from hvc_instantiate(), but that's only used in the early console case. In hvc_alloc(), register_console() was not called. Add a call to register_console() in hvc_alloc(), set up the index in th

Re: BUG: scheduling while atomic:

2011-10-05 Thread Scott Wood
On 10/05/2011 06:24 AM, smitha.va...@wipro.com wrote: > Hi Scoot, > > When my ISR gets exeuted I get a below BUG. Could let me what I am > doing wrong in the ISR? > > > BUG: scheduling while atomic: IRQ-20/0x0fff/108 > Call Trace: > [C3AEFEC0] [C0007CCC] (unreliable) > [C3AEFEF0] [C001

Re: Defintion of kernstart_addr

2011-10-05 Thread Dave Hansen
On Wed, 2011-10-05 at 18:19 +0530, Suzuki Poulose wrote: > #define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) - > PHYSICAL_START + KERNELBASE) > > where, > PHYSICAL_START is #define'd to kernstart_addr variable, updated at > boot Wh

RE: scheduling while atomic:

2011-10-05 Thread David Laight
Not entirely relevant to the error you are seeing, but your ISR is: > irqreturn_t cpld_irq_handler(int irq, void * dev_id, struct pt_regs *regs) > { > wake_up(&cpld_intr_wait); > atomic_inc(&cpld_intr_data); /* incrementing this will indicate the poll() that

Re: [patch 0/4] powerpc: Mark various interrupts IRQF_NO_THREAD

2011-10-05 Thread Thomas Gleixner
On Wed, 5 Oct 2011, Gabriel Paubert wrote: > On Wed, Oct 05, 2011 at 12:30:49PM -, Thomas Gleixner wrote: > > The following series marks the obvious interrupts IRQF_NO_THREAD to > > prevent forced interrupt threading - no guarantee of completeness :) > > > > The last patch enables the forced

Re: [patch 0/4] powerpc: Mark various interrupts IRQF_NO_THREAD

2011-10-05 Thread Gabriel Paubert
On Wed, Oct 05, 2011 at 12:30:49PM -, Thomas Gleixner wrote: > The following series marks the obvious interrupts IRQF_NO_THREAD to > prevent forced interrupt threading - no guarantee of completeness :) > > The last patch enables the forced threading mechanism in the core > code, which in turn

Defintion of kernstart_addr

2011-10-05 Thread Suzuki Poulose
Hi Kumar, I have been working on the CONFIG_RELOCATABLE support for PPC44x, trying to process the relocations generated by the compiler. Since the TLB size is 256M, we cannot enforce a page aligned kernel load address. I came across some issues with the __va() / __pa() translations, while the

[patch 2/4] powerpc: wsp: Mark opb cascade handler IRQF_NO_THREAD

2011-10-05 Thread Thomas Gleixner
Cascade handlers must run in hard interrupt context. Signed-off-by: Thomas Gleixner --- arch/powerpc/platforms/wsp/opb_pic.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Index: linux-2.6/arch/powerpc/platforms/wsp/opb_pic.c =

[patch 1/4] powerpc: 85xx: Mark cascade irq IRQF_NO_THREAD

2011-10-05 Thread Thomas Gleixner
Cascade interrupt must run in hard interrupt context. Signed-off-by: Thomas Gleixner --- arch/powerpc/platforms/85xx/mpc85xx_cds.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Index: linux-2.6/arch/powerpc/platforms/85xx/mpc85xx_cds.c

[patch 0/4] powerpc: Mark various interrupts IRQF_NO_THREAD

2011-10-05 Thread Thomas Gleixner
The following series marks the obvious interrupts IRQF_NO_THREAD to prevent forced interrupt threading - no guarantee of completeness :) The last patch enables the forced threading mechanism in the core code, which in turn enables the "irqthreaded" commandline option. Thanks, tglx ___

[patch 3/4] powerpc: Mark IPI interrupts IRQF_NO_THREAD

2011-10-05 Thread Thomas Gleixner
IPI handlers cannot be threaded. Remove the obsolete IRQF_DISABLED flag (see commit e58aa3d2) while at it. Signed-off-by: Thomas Gleixner --- arch/powerpc/kernel/smp.c |2 +- arch/powerpc/platforms/powermac/smp.c |4 ++-- arch/powerpc/sysdev/xics/xics-common.c |6 +++---

[patch 4/4] powerpc: Allow irq threading

2011-10-05 Thread Thomas Gleixner
All interrupts which must be non threaded are marked IRQF_NO_THREAD. So it's safe to allow force threaded handlers. Signed-off-by: Thomas Gleixner --- arch/powerpc/Kconfig |1 + 1 file changed, 1 insertion(+) Index: linux-2.6/arch/powerpc/Kconfig

BUG: scheduling while atomic:

2011-10-05 Thread smitha.vanga
Hi Scoot, When my ISR gets exeuted I get a below BUG. Could let me what I am doing wrong in the ISR? BUG: scheduling while atomic: IRQ-20/0x0fff/108 Call Trace: [C3AEFEC0] [C0007CCC] (unreliable) [C3AEFEF0] [C0017F10] [C3AEFF00] [C0268818] [C3AEFF50] [C0017F44] [C3AEFF60] [C0018044] [C3

Re: [PATCH] mlx4_en: fix transmit of packages when blue frame is enabled

2011-10-05 Thread Eli Cohen
On Tue, Oct 04, 2011 at 05:26:20PM -0300, Thadeu Lima de Souza Cascardo wrote: I believe we have an endianess problem here. The source buffer is in big endian - in x86 archs, it will rich the pci device unswapped since both x86 and pci are little endian. In ppc, it wil be swapped by the chipset so