Re: [RFC] Inter-processor Mailboxes Drivers

Hi, On Sat, Feb 12, 2011 at 2:49 AM, Meador Inge wrote: > >    1. Hardware specific bits somewhere under '.../arch/*'.  Drivers >       for the MPIC message registers on Power and OMAP4 mailboxes, for >       example. Yes; this can help. >    2. A higher level driver under '.../drivers/mailbox/

[PATCH RFCv7 1/2] misc: add CARMA DATA-FPGA Access Driver

This driver allows userspace to access the data processing FPGAs on the OVRO CARMA board. It has two modes of operation: 1) random access This allows users to poke any DATA-FPGA registers by using mmap to map the address region directly into their memory map. 2) correlation dumping When correla

[PATCH RFCv7 2/2] misc: add CARMA DATA-FPGA Programmer support

This adds support for programming the data processing FPGAs on the OVRO CARMA board. These FPGAs have a special programming sequence that requires that we program the Freescale DMA engine, which is only available inside the kernel. Signed-off-by: Ira W. Snyder --- drivers/misc/carma/Kconfig

[PATCH RFCv7 0/2] CARMA Board Support

Hello everyone, This is the seventh posting of these drivers, taking into account comments from earlier postings. I've made sure that the drivers both pass checkpatch without any errors or warnings. I would appreciate as much review as you can offer, so that these can get into the next merge cycle

Re: Question on setting up external interrupt for P1020 (MPC8xxx) with device tree

On Fri, 11 Feb 2011 17:15:47 -0500 Kenny Ho wrote: > Thanks Scott. > > Do you know the logic of the hwirq <-> virq mapping? It's dynamic. > When I was digging into the GPIO interrupt, the hwirq seems to be the same as > the virq The allocator tries that if it's available, but if that virq is

RE: Question on setting up external interrupt for P1020 (MPC8xxx) with device tree

Thanks Scott. Do you know the logic of the hwirq <-> virq mapping? When I was digging into the GPIO interrupt, the hwirq seems to be the same as the virq (both are 47 which is 16 (external interrupt) + 31 (internal interrupt). If I want to use external interrupt 7 and 8, should the virq also be 7

Re: Question on setting up external interrupt for P1020 (MPC8xxx) with device tree

On Fri, 11 Feb 2011 14:07:26 -0500 Kenny Ho wrote: > Hi, > > > > I am trying to write a device driver that uses an external interrupt > (one of the 16 irq lines) for the Freescale P1020 processor and I hope > some of you can help. Am I suppose to setup a separate node in the dts > and look f

Question on setting up external interrupt for P1020 (MPC8xxx) with device tree

Hi, I am trying to write a device driver that uses an external interrupt (one of the 16 irq lines) for the Freescale P1020 processor and I hope some of you can help. Am I suppose to setup a separate node in the dts and look for that node in my driver to setup the interrupt? Or does the dts in

[RFC] Inter-processor Mailboxes Drivers

Hi All, I am currently working on building AMP systems using OpenMCAPI (https://bitbucket.org/hollisb/openmcapi/wiki/Home) as the inter-processor communication mechanism. With OpenMCAPI we, of course, need a way to send messages to various cores. On some Freescale PPC platforms (e.g. P1022DS, M

Re: BootX

Hi, I have looked at the -S output for mesh.c from both 4.1.2 and 4.3.5. The generated code is quite different but I can not see any difference that is causing the problem? If I read and print the bus status register 0, it does appear to have the busy bit set? I'm in way over my head here. It ap

Re: [PATCH v3 0/4] powerpc: Open PIC binding and "pic-no-reset"

On Fri, Feb 11, 2011 at 11:41 AM, Scott Wood wrote: > On Fri, 11 Feb 2011 14:58:13 + > Yoder Stuart-B08248 wrote: > >> >> >> > -Original Message- >> > From: Meador Inge [mailto:mead...@gmail.com] >> > Sent: Thursday, February 10, 2011 9:26 PM >> > To: Benjamin Herrenschmidt >> > Cc: Y

Re: [PATCH v3 0/4] powerpc: Open PIC binding and "pic-no-reset"

On Fri, 11 Feb 2011 14:58:13 + Yoder Stuart-B08248 wrote: > > > > -Original Message- > > From: Meador Inge [mailto:mead...@gmail.com] > > Sent: Thursday, February 10, 2011 9:26 PM > > To: Benjamin Herrenschmidt > > Cc: Yoder Stuart-B08248; devicetree-disc...@lists.ozlabs.org; linuxp

RE: [PATCH V8 03/10] USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer

> > > dwc_read_reg32 is used nowhere throughout the code. One of dwc_read32 > > and > > dwc_read_reg32 should be removed IMO. There was once only > > dwc_read_reg32. In > > version 5 of your patchset I believe. Why did you add another function? > > AFAIK it is not correct to store pointers in u32 b

Re: [PATCH v3 0/4] powerpc: Open PIC binding and "pic-no-reset"

On 02/11/2011 08:58 AM, Yoder Stuart-B08248 wrote: -Original Message- From: Meador Inge [mailto:mead...@gmail.com] Sent: Thursday, February 10, 2011 9:26 PM To: Benjamin Herrenschmidt Cc: Yoder Stuart-B08248; devicetree-disc...@lists.ozlabs.org; linuxppc- d...@lists.ozlabs.org Subject:

RE: [PATCH v3 0/4] powerpc: Open PIC binding and "pic-no-reset"

> -Original Message- > From: Meador Inge [mailto:mead...@gmail.com] > Sent: Thursday, February 10, 2011 9:26 PM > To: Benjamin Herrenschmidt > Cc: Yoder Stuart-B08248; devicetree-disc...@lists.ozlabs.org; linuxppc- > d...@lists.ozlabs.org > Subject: Re: [PATCH v3 0/4] powerpc: Open PIC bi

Re: [RFC] dt: add of_platform_bus_snoop() which attaches nodes to devices

Hi Grant, On 1 February 2011 03:31, Grant Likely wrote: > This patch implements an alternate method for using device tree data > for populating machine device registration.  Traditionally, board > support has directly generated and registered devices based on nodes > in the device tree.  The boar