Yestersday's linux-next(2.6.35_next_20100802) build fails with the following
error on both system p and x.
drivers/net/ixgbe/ixgbe_main.c: In function 'ixgbe_select_queue':
drivers/net/ixgbe/ixgbe_main.c:6159: error: 'struct ixgbe_fcoe' has no member
named 'up'
drivers/net/ixgbe/ixgbe_ma
> I'm trying to relocate the bootwrapper from the default address
> (0x40) to a higher address (e.g. 0x80) in order to support a
> larger than 4MB initramfs. However the kernel panic when trying to
> access the device tree blob which was relocated accordingly to a
> higher address. The kern
On Tue, 03 Aug 2010 08:44:16 -0500
Nathan Fontenot wrote:
> Update the memory hotplug documentation to reflect the new behaviors of
> memory blocks reflected in sysfs.
>
> Signed-off-by: Nathan Fontenot
Acked-by: KAMEZAWA Hiroyuki
A request from me:
Could you clarify what happens if there
On Tue, 03 Aug 2010 08:42:35 -0500
Nathan Fontenot wrote:
> Update the node sysfs code to be aware of the new capability for a memory
> block to contain multiple memory sections. This requires an additional
> parameter to unregister_mem_sect_under_nodes so that we know which memory
> section of
On Tue, 03 Aug 2010 08:41:45 -0500
Nathan Fontenot wrote:
> Update the find_memory_block declaration to to take a struct mem_section *
> so that it matches the definition.
>
> Signed-off-by: Nathan Fontenot
Acked-by: KAMEZAWA Hiroyuki
Hmm...my mmotm-0727 has this definition in memory.h...
e
On Tue, 03 Aug 2010 08:40:49 -0500
Nathan Fontenot wrote:
> Update the memory sysfs code that each sysfs memory directory is now
> considered a memory block that can contain multiple memory sections per
> memory block. The default size of each memory block is SECTION_SIZE_BITS
> to maintain the
I've got custom boards that have been running for a while on rev A
460ex parts but when the rev B parts became available some problems
surfaced. We are trying to work around the issues in software. To make
this simple, I've got 2 460exs connected together via PCI and PCIe so i
can switch the
On Tue, 03 Aug 2010 08:39:50 -0500
Nathan Fontenot wrote:
> Add a new mutex for use in adding and removing of memory blocks. This
> is needed to avoid any race conditions in which the same memory block could
> be added and removed at the same time.
>
> Signed-off-by: Nathan Fontenot
Acked-by:
On Tue, 03 Aug 2010 08:38:37 -0500
Nathan Fontenot wrote:
> Add a section count property to the memory_block struct to track the number
> of memory sections that have been added/removed from a memory block. This
> allows us to know when the last memory section of a memory block has been
> removed
On Tue, 03 Aug 2010 08:37:31 -0500
Nathan Fontenot wrote:
> Update the 'phys_index' properties of a memory block to include a
> 'start_phys_index' which is the same as the current 'phys_index' property.
> The property still appears as 'phys_index' in sysfs but the memory_block
> struct name is up
On Tue, 03 Aug 2010 08:36:39 -0500
Nathan Fontenot wrote:
> Move the find_memory_block() routine up to avoid needing a forward
> declaration in subsequent patches.
>
> Signed-off-by: Nathan Fontenot
Acked-by: KAMEZAWA Hiroyuki
___
Linuxppc-dev mail
On 07/23/2010 12:07 AM, Vaidyanathan Srinivasan wrote:
* Benjamin Herrenschmidt [2010-07-23 15:11:00]:
On Fri, 2010-07-23 at 10:38 +0530, Vaidyanathan Srinivasan wrote:
Yes. extended_cede_processor() will return with interrupts enabled in
the cpu. (This is done by the hypervisor). Under nor
On Fri, Jun 11, 2010 at 04:59:46PM -0600, Grant Likely wrote:
> I've been doing a bit of work on some introductory level documentation
> of the flattened device tree. I've got a rough copy up on the
> devicetree.org wiki, and I could use some feedback. If anyone has
> some time to look at it, you
From: Signed-off-by: Darren Hart
All IRQs are migrated away from a CPU that is being offlined so the
following messages suggest a problem when the system is behaving as
designed:
IRQ 262 affinity broken off cpu 1
IRQ 17 affinity broken off cpu 0
IRQ 18 affinity broken off cpu 0
IRQ 19 affinity b
From: Signed-off-by: Darren Hart
During CPU offline/online tests __cpu_up would flood the logs with
the following message:
Processor 0 found.
This provides no useful information to the user as there is no context
provided, and since the operation was a success (to this point) it is expected
tha
From: Signed-off-by: Darren Hart
start_secondary() is called shortly after _start and also via
cpu_idle()->cpu_die()->pseries_mach_cpu_die()
start_secondary() expects a preempt_count() of 0. pseries_mach_cpu_die() is
called via the cpu_idle() routine with preemption disabled, resulting in the
f
The following patch series addresses several issues detected during intense CPU
offline/online testing on the mainline kernel with CONFIG_PREEMPT=y. These
patches require the following patch from Brian King:
http://patchwork.ozlabs.org/patch/59645/
Tested against linux-2.6.git master with and wit
Hi.. all
I'm porting the linux 2.6.27 kernel to the custom board with Freescale8270.
The base is the pq2fads board. The board is noproblem with linux-2.6.17.1
and linux-2.6.25.
When booting this machine, a crash takes place such as :
Hi,
I'm trying to relocate the bootwrapper from the default address
(0x40) to a higher address (e.g. 0x80) in order to support a
larger than 4MB initramfs. However the kernel panic when trying to
access the device tree blob which was relocated accordingly to a
higher address. The kernel me
In message <0ce8b6be3c4ad74ab97d9d29bd24e55201143...@corpexch1.na.ads.idt.com>
you wrote:
> Yang Li pointed to these patches in his post from July 23, 2010.
> It would be nice to have these patches in mainline code.=20
This is still broken in Kumar's latest tree. Do you guys wanna repost
them
(Ping Milton...)
On 07/29/10 14:42, Cong Wang wrote:
On 07/27/10 18:00, Milton Miller wrote:
[ Added kexec at lists.infradead.org and linuxppc-dev@lists.ozlabs.org ]
Currently KEXEC_SEGMENT_MAX is only 16 which is too small for machine
with
many memory ranges. When hibernate on a machine wit
> -Original Message-
> From: glik...@secretlab.ca [mailto:glik...@secretlab.ca] On
> Behalf Of Grant Likely
> Sent: Thursday, August 05, 2010 9:03 AM
> To: Zang Roy-R61911
> Cc: linux-...@vger.kernel.org; linuxppc-...@ozlabs.org;
> a...@linux-foundation.org
> Subject: Re: [PATCH 1/3 v2
On Wed, 2010-08-04 at 10:49 -0400, Neil Horman wrote:
> Ping yet again. Ben, This needs review/acceptance from you or Paul
> Neil
Isn't it already in powerpc-next about to be pulled by Linus ?
In general, I recommend you check the status of your patches on
patchwork. I'm nagging Jeremy to add a
Hi Linus !
Here's the batch of powerpc stuff for this merge window. Not major highlight,
some work on 64-bit Book3E (embedded) by myself, and the powerpc part of the
HW breakpoint stuff by Mohan Kumar and Paulus, and the usual batch of embedded
bits and pieces.
This does -not- include my memblock
On Mon, Aug 2, 2010 at 9:11 PM, Roy Zang wrote:
> From: Jerry Huang
>
> Add auto CMD12 command support for eSDHC driver.
> This is needed by P4080 and P1022 for block read/write.
> Manual asynchronous CMD12 abort operation causes protocol violations on
> these silicons.
>
> Signed-off-by: Jerry H
On Mon, Aug 2, 2010 at 9:11 PM, Roy Zang wrote:
> Signed-off-by: Roy Zang
> ---
> Documentation/powerpc/dts-bindings/fsl/esdhc.txt | 2 ++
> arch/powerpc/boot/dts/p4080ds.dts | 1 +
> 2 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/Documentation/powerpc/dts
On Tue, Aug 3, 2010 at 1:50 PM, Julia Lawall wrote:
> From: Julia Lawall
>
> for_each_node_by_name only exits when its first argument is NULL, and a
> subsequent call to of_node_put on that argument is unnecessary.
>
> The semantic patch that makes this change is as follows:
> (http://coccinelle.
Add support for adding "status = disabled" to an SSI node to incidate that it
is not wired on the board. This replaces the not-so-intuitive previous method
of omitting a codec-handle property.
Signed-off-by: Timur Tabi
---
Kumar, would you please ACK the device-tree portion of this patch? I wa
The following changes since commit e8e5c2155b0035b6e04f29be67f6444bc914005b:
Matt Evans (1):
powerpc/kexec: Fix orphaned offline CPUs across kexec
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
Anton Vorontsov (3):
p
On Sun, 2010-07-11 at 02:49 -0500, Milton Miller wrote:
> On Fri, 09 Jul 2010 about 08:55:01 -, Will Schmidt wrote:
> > We've been seeing some issues with userspace randomly SIGSEGV'ing while
> > running the -RT kernels on POWER7 based systems. After lots of
> > debugging, head scratching, an
On Mar 23, 2010, at 2:57 AM, Heiko Schocher wrote:
> Supported SMC1 (serial console), SCC1 Ethernet (10Mbps HD).
> FEC Ethernet, 8MB NOR CFI Flash.
>
> Tested on STK8xx with TQM860L (with FEC)
> and with TQM855M (without FEC).
>
> Signed-off-by: Heiko Schocher
> ---
> - based against git://git
On Jul 21, 2010, at 5:04 PM, Bradley Hughes wrote:
> This version uses "fsl,mpc8555..." instead of "fsl,85..." notation.
>
> There is also an 8541 version of this board so DTS for this board
> is specific to the 8555 processor.
>
> Another patch is coming to fix-up other DTS that use old notati
On Jul 21, 2010, at 5:04 PM, Bradley Hughes wrote:
> The "fsl,85..." style compatible binding was to be deprecated
> some time ago. This patch corrects existing occurrences of
> the incorrect binding. The memory-controller and
> l2-cache-controller are the only affected nodes.
>
> Signed-off-b
On Jul 21, 2010, at 3:33 PM, Dmitry Eremin-Solenikov wrote:
> By default ti1520 bridge expects an input clock on CLOCK pin (to control
> power chip). However on this boards CLOCK should be generated by PCI1520
> itself. Add a quirk that enables internal 16 KHz clock generation on
> this pin.
>
>
On Jul 2, 2010, at 5:25 PM, Timur Tabi wrote:
> Introduce basic support for the Freescale P1022DS reference board, based on
> the
> Freescale BSP for this board. This patch excludes the DIU, SSI, and MMC/SD
> drivers. Only a 36-bit DTS is provided.
>
> Update mpc86xx_smp_defconfig and mpc85xx
On Jul 21, 2010, at 3:33 PM, Dmitry Eremin-Solenikov wrote:
> By default ti1520 bridge expects an input clock on CLOCK pin (to control
> power chip). However on this boards CLOCK should be generated by PCI1520
> itself. Add a quirk that enables internal 16 KHz clock generation on
> this pin.
>
>
On Jul 21, 2010, at 3:33 PM, Dmitry Eremin-Solenikov wrote:
> Update PCI IRQ mapping on TQM85xx platforms: include INTC and INTD on PCI-X
> slot and add INTA/INTB mapping for PCMCIA bridge.
>
> Signed-off-by: Dmitry Eremin-Solenikov
> ---
> arch/powerpc/boot/dts/tqm8540.dts |9
On Jul 8, 2010, at 3:10 PM, Ilya Yanok wrote:
> This patch adds support for MPC8308RDB development board from
> Freescale.
> Supported devices:
> DUART
> Dual Ethernet
> NOR and NAND flashes
> I2C
> USB in peripheral mode
>
> PCIE support is broken by the commit 3da34aa ("powerpc/fsl: Support
>
On Jul 8, 2010, at 3:10 PM, Ilya Yanok wrote:
> This patch adds the quirk for PCIE controller found on Freescale MPC8308.
> The quirk is the same as for other MPC83xx processors.
>
> Signed-off-by: Ilya Yanok
> ---
> arch/powerpc/sysdev/fsl_pci.c |1 +
> include/linux/pci_ids.h |1
On Jun 8, 2010, at 2:55 PM, Anton Vorontsov wrote:
> The mpc85xx_mds_setup_arch() function is incomprehensible
> and unmaintainable. Factor out all QE specific stuff into
> mpc85xx_mds_qe_init() and mpc85xx_mds_reset_ucc_phys().
>
> Also move QE stuff out of mpc85xx_mds_pic_init().
>
> The diff
On Jun 8, 2010, at 2:55 PM, Anton Vorontsov wrote:
> P1021 processors have no dedicated ROM to store the QE microcode,
> so the fimrware is stored externally, and it is U-Boot responsibility
> to load it. It might be that the board is booting without QE, e.g.
> currently U-Boot doesn't support QE
On Jun 8, 2010, at 2:55 PM, Anton Vorontsov wrote:
> The code inside '#ifdef CONFIG_QUICC_ENGINE' makes the
> mpc85xx_mds_setup_arch() return early if no QE nodes present,
> and so SWIOTLB is never initialized.
>
> This patch fixes the issue by moving SWIOTLB code above
> QE.
>
> Signed-off-by:
On Wed, 4 Aug 2010 15:34:59 +0100
"Jenkins, Clive" wrote:
> > I am trying to boot MPC8377ERBD freescale board from NAND flash.
> > As per its specifications, it supports NAND boot but it there is
> > no support for NAND boot in the BSP(confirmed with freescale also).
> > Now I decided to modify B
Peter/Li,
Did you get a chance to see this ?
Regards--
Subrata
On Mon, 2010-08-02 at 14:22 +0530, Subrata Modak wrote:
> Hi,
>
> The following suspicious rcu_dereference_check() usage is detected
> during 2.6.35-stable boot on my ppc64/p7 machine:
>
> ==
> I am trying to boot MPC8377ERBD freescale board from NAND flash.
> As per its specifications, it supports NAND boot but it there is
> no support for NAND boot in the BSP(confirmed with freescale also).
> Now I decided to modify BSP myself to support NAND boot and I am
> confused that from where s
On Tue, Jul 13, 2010 at 09:46:09AM -0400, Neil Horman wrote:
> Hey all-
> About 2 years ago now, I sent this patch upstream to allow makedumpfile
> to properly filter cores on ppc64:
> http://www.mail-archive.com/ke...@lists.infradead.org/msg02426.html
> It got acks from the kexec folks so I
On Wed, 4 Aug 2010 15:16:34 +0200
"Roedel, Joerg" wrote:
> On Mon, Aug 02, 2010 at 07:55:03AM -0400, FUJITA Tomonori wrote:
> > I guess that this driver does a partial sync with
> > dma_sync_single_for_* API. dma-debug can't handle it properly. It's
> > likely that this is a false warning.
>
> I
On 07/22/2010 03:25 PM, Benjamin Herrenschmidt wrote:
On Thu, 2010-07-22 at 11:24 -0700, Darren Hart wrote:
1) How can the preempt_count() get mangled across the H_CEDE hcall?
2) Should we call preempt_enable() in cpu_idle() prior to cpu_die() ?
The preempt count is on the thread info at the
On Mon, Aug 02, 2010 at 07:55:03AM -0400, FUJITA Tomonori wrote:
> I guess that this driver does a partial sync with
> dma_sync_single_for_* API. dma-debug can't handle it properly. It's
> likely that this is a false warning.
If this turns out to be true it is not trivial to fix. I prepare a patch
Hi,
I am trying to boot MPC8377ERBD freescale board from NAND flash. As per its
specifications, it supports NAND boot but it there is no support for NAND
boot in the BSP(confirmed with freescale also). Now I decided to modify BSP
myself to support NAND boot and I am confused that from where should
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