Many a times, the requested breakpoint length can be less than the fixed
breakpoint length i.e. 8 bytes supported by PowerPC BookIII S. This could lead
to extraneous interrupts resulting in false breakpoint notifications. The patch
below detects and discards such interrupts for non-ptrace requests
A signal delivered between a hw_breakpoint_handler() and the
single_step_dabr_instruction() will not have the breakpoint active during
signal handling (since breakpoint will not be restored through single-stepping
due to absence of MSR_SE bit on the signal frame). Enable breakpoints before
signal d
An alignment interrupt may intervene between a DSI/hw-breakpoint exception
and the single-step exception. Enable the alignment interrupt (through
modifications to emulate_single_step()) to notify the single-step exception
handler for proper restoration of hw-breakpoints.
Signed-off-by: K.Prasad
-
Implement perf-events based hw-breakpoint interfaces for PowerPC Book III S
processors. These interfaces help arbitrate requests from various users and
schedules them as appropriate.
Signed-off-by: K.Prasad
---
arch/powerpc/Kconfig |1
arch/powerpc/include/asm/cputable.h
Hi All,
Please find a new set of patches that have the following changes.
Changelog - ver XXII
(Version XXI: linuxppc-dev ref:20100525091314.ga29...@in.ibm.com)
- Extraneous breakpoint exceptions are now properly handled; causative
instruction will be single-stepped
Certain architectures (such as PowerPC Book III S) have a need to cleanup
data-structures before the breakpoint is unregistered. This patch introduces
an arch-specific hook in release_bp_slot() along with a weak definition in
the form of a stub funciton.
Signed-off-by: K.Prasad
Acked-by: Frederic
On Fri, May 28, 2010 at 02:23:30PM +1000, Michael Neuling wrote:
>
>
> In message <20100528041645.gb25...@in.ibm.com> you wrote:
> > On Fri, May 28, 2010 at 12:28:43PM +1000, Michael Neuling wrote:
> > >
> > >
> > > In message <20100527141203.ga20...@in.ibm.com> you wrote:
> > > > Hi Paul,
> >
On Fri, May 28, 2010 at 12:05:56PM +1000, Paul Mackerras wrote:
> On Thu, May 27, 2010 at 07:42:03PM +0530, Ananth N Mavinakayanahalli wrote:
>
> > While we are at it, can we also add nop to the list of emulated
> > instructions?
>
> I have a patch in development that emulates most of the arithme
Hi Steven,
After merging the final tree, today's linux-next build (powerpc allyesconfig)
failed like this:
arch/powerpc/platforms/pseries/hvCall_inst.c: In function 'hcall_inst_init':
arch/powerpc/platforms/pseries/hvCall_inst.c:143: warning: passing argument 1
of 'register_trace_hcall_entry' f
In message <20100528041645.gb25...@in.ibm.com> you wrote:
> On Fri, May 28, 2010 at 12:28:43PM +1000, Michael Neuling wrote:
> >
> >
> > In message <20100527141203.ga20...@in.ibm.com> you wrote:
> > > Hi Paul,
> > >
> > > While we are at it, can we also add nop to the list of emulated
> > > in
On Fri, May 28, 2010 at 12:28:43PM +1000, Michael Neuling wrote:
>
>
> In message <20100527141203.ga20...@in.ibm.com> you wrote:
> > Hi Paul,
> >
> > While we are at it, can we also add nop to the list of emulated
> > instructions?
> >
> > Ananth
> > ---
> > From: Ananth N Mavinakayanahalli
>
On Thu, May 27, 2010 at 03:22:45PM -0500, Kumar Gala wrote:
>
> On May 27, 2010, at 9:12 AM, Ananth N Mavinakayanahalli wrote:
>
> > Hi Paul,
> >
> > While we are at it, can we also add nop to the list of emulated
> > instructions?
>
> Dare I ask why we need to emulate nop?
We are close to get
In message <20100527141203.ga20...@in.ibm.com> you wrote:
> Hi Paul,
>
> While we are at it, can we also add nop to the list of emulated
> instructions?
>
> Ananth
> ---
> From: Ananth N Mavinakayanahalli
>
> Emulate ori 0,0,0 (nop).
>
> The long winded way is to do:
>
> case 24:
>
On Thu, May 27, 2010 at 07:42:03PM +0530, Ananth N Mavinakayanahalli wrote:
> While we are at it, can we also add nop to the list of emulated
> instructions?
I have a patch in development that emulates most of the arithmetic,
logical and shift/rotate instructions, including ori.
While you're her
Enables support for HMC initiated partition hibernation. This is
a firmware assisted hibernation, since the firmware handles writing
the memory out to disk, along with other partition information,
so we just mimic suspend to ram.
Signed-off-by: Brian King
---
arch/powerpc/Kconfig
Partition hibernation will use some of the same code as is
currently used for Live Partition Migration. This function
further abstracts this code such that code outside of rtas.c
can utilize it. It also changes the error field in the suspend
me data structure to be an atomic type, since it is set
On May 27, 2010, at 9:12 AM, Ananth N Mavinakayanahalli wrote:
> Hi Paul,
>
> While we are at it, can we also add nop to the list of emulated
> instructions?
Dare I ask why we need to emulate nop?
- k
>
> Ananth
> ---
> From: Ananth N Mavinakayanahalli
>
> Emulate ori 0,0,0 (nop).
>
> The
Fix smatch warning: warning: constant 0x8 is so big it is long
Signed-off-by: Denis Kirjanov
---
arch/powerpc/platforms/cell/iommu.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/cell/iommu.c
b/arch/powerpc/platforms/cell/iommu.c
index
Hi all,
on the embedded system I'm working (mpc5121e, linux kernel 2.6.24.6) when I
type the command "halt" on the console I see a broadcast message sent to all
the users like this:
" Broadcast message from root (console) (Thu May 27 09:04:41 2010):
The system is going down for system halt NOW!
Hi all,
on the embedded system I'm working (mpc5121e, linux kernel 2.6.24.6) when I
type the command "halt" on the console I see a broadcast message sent to all
the users like this:
" Broadcast message from root (console) (Thu May 27 09:04:41 2010):
The system is going down for system halt NOW!
Hi Paul,
While we are at it, can we also add nop to the list of emulated
instructions?
Ananth
---
From: Ananth N Mavinakayanahalli
Emulate ori 0,0,0 (nop).
The long winded way is to do:
case 24:
rd = (instr >> 21) & 0x1f;
if (rd != 0)
> -Original Message-
> From: David Miller [mailto:da...@davemloft.net]
> Sent: Wednesday, May 26, 2010 9:45 PM
> To: John Linn
> Cc: net...@vger.kernel.org; linuxppc-...@ozlabs.org;
grant.lik...@secretlab.ca;
> jwbo...@linux.vnet.ibm.com; john.willi...@petalogix.com;
michal.si...@petalogix.
The RAS code has a #define, RAS_VECTOR_OFFSET, that's used in the
check-exception RTAS call for the vector offset of the exception.
We'll be using this same vector offset for the upcoming IO Event interrupts
code (0x500) so let's move it to include/asm/rtas.h and call it
RTAS_VECTOR_EXTERNAL_INTER
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