Form 1 affinity allows multiple entries in ibm,associativity-reference-points
which represent affinity domains in decreasing order of importance. The
Linux concept of a node is always the first entry, but using the other
values as an input to node_distance() allows the memory allocator to make
bet
Firmware changed the way it represents memory and cpu affinity on POWER7.
Unfortunately the old method now caps the topology to work around issues
with legacy operating systems. For Linux to get the correct topology we
need to use the new form 1 affinity information.
We set the form 1 field in th
I noticed /proc/sys/vm/zone_reclaim_mode was 0 on a ppc64 NUMA box. It gets
enabled via this:
/*
* If another node is sufficiently far away then it is better
* to reclaim pages in a zone before going off node.
*/
if (distance > RECLAIM_DISTANCE)
On Thu, Apr 29, 2010 at 6:49 PM, Anatolij Gustschin wrote:
> +void __init mpc5121_ads_init_early(void)
> +{
> + mpc512x_init_diu();
> +}
> +
> define_machine(mpc5121_ads) {
> .name = "MPC5121 ADS",
> .probe = mpc5121_ads_probe,
> .se
On Thu, Apr 29, 2010 at 6:49 PM, Anatolij Gustschin wrote:
> +Optional properties:
> +- EDID : verbatim EDID data block describing attached display.
> + Data from the detailed timing descriptor will be used to
> + program the display controller.
The property name should be lower-case.
> /*
>
On Thu, Apr 29, 2010 at 6:49 PM, Anatolij Gustschin wrote:
> This patch series rework DIU support patches submitted
> previously. Comments to the previos patch series have
> been addressed, not related changes are dropped and some
> changes are split out to separate patches to simplify
> review. F
In kernel source, default kernel stack size for PPC32 is as follows:
#if defined(CONFIG_PPC64)
#define THREAD_SHIFT14
#elif defined(CONFIG_PPC_256K_PAGES)
#define THREAD_SHIFT15
#else
#define THREAD_SHIFT13
#endif
#define THREAD_SIZE (1 << THREAD_SHI
MPC5121 DIU configuration/setup as initialized by the boot
loader currently will get lost while booting Linux. As a
result displaying the boot splash is not possible through
the boot process.
To prevent this we reserve configured DIU frame buffer
address range while booting and preserve AOI descri
Adds support for encoding display mode information
in the device tree using verbatim EDID block.
If the EDID entry in the DIU node is present, the
driver will build mode database using EDID data
and allow setting the display modes from this database.
Otherwise display mode will be set using mode
e
Update compatible and interrupt properties description.
Furthermore an example for the MPC5121 has been added.
Signed-off-by: Anatolij Gustschin
---
Documentation/powerpc/dts-bindings/fsl/diu.txt | 14 --
1 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/Documentation
This patch series rework DIU support patches submitted
previously. Comments to the previos patch series have
been addressed, not related changes are dropped and some
changes are split out to separate patches to simplify
review. Furthermore a patch has been added to support
setting display mode usin
Some DIU structures will be used in platform code in
subsequent MPC5121 DIU patch, so we move this header
to be able to include it elsewhere.
Signed-off-by: Anatolij Gustschin
---
drivers/video/fsl-diu-fb.c|2 +-
{drivers/video => include/linux}/fsl-diu-fb.h |0
2 fil
On MPC5121 re-configuring the DIU area descriptor by writing
new descriptor address doesn't work. As a result, DIU continues
to display using old area descriptor even if the new one has
been set.
Disabling the DIU before setting the new descriptor and
subsequently enabling it fixes the problem.
S
On Thu, 2010-04-29 at 10:11 -0700, Mike Kravetz wrote:
> On Fri, Apr 23, 2010 at 05:04:35PM -0500, Tseng-Hui (Frank) Lin wrote:
> > Add Power7 icswx co-processor instruction support.
>
> Silly question perhaps, but
>
> Do we want this code to be enabled/exist for all processors? I don't
> see an
On Fri, Apr 23, 2010 at 05:04:35PM -0500, Tseng-Hui (Frank) Lin wrote:
> Add Power7 icswx co-processor instruction support.
Silly question perhaps, but
Do we want this code to be enabled/exist for all processors? I don't
see any checks for Power7 processors. Or, will it be the responsibility
of
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