On Mon, Apr 19, 2010 at 10:46 AM, Michael Ellerman
wrote:
> On Fri, 2010-04-16 at 15:34 +0800, Li Yang wrote:
>> From: Zhao Chenhui
>>
>> Put all fsl_msi banks in a linked list. The list of banks then can be
>> traversed when allocating new msi interrupts.
>
> So there are multiple banks, and you
On Mon, Apr 19, 2010 at 10:34 AM, Michael Ellerman
wrote:
> On Fri, 2010-04-16 at 15:34 +0800, Li Yang wrote:
>> From: Zhao Chenhui
>>
>> Make a single PCIe MSI bank shareable through CAMP OSes. The number of
>> MSI used by each core can be configured by dts file.
>>
>> Signed-off-by: Zhao Chenhu
The e1000e device is becoming more common these days, so let's just
build it in for pseries & ppc64_defconfig.
Signed-off-by: Michael Neuling
---
arch/powerpc/configs/ppc64_defconfig |2 +-
arch/powerpc/configs/pseries_defconfig |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
On 4/19/2010 10:40 AM, Michael Ellerman wrote:
On Fri, 2010-04-16 at 15:34 +0800, Li Yang wrote:
From: Zhao Chenhui
In fsl_of_msi_probe(), the virt_msir's chip_data have been stored
the pointer to struct mpic. We add a struct fsl_msi_cascade_data
to store the pointer to struct fsl_msi and m
On Fri, 2010-04-16 at 15:34 +0800, Li Yang wrote:
> From: Zhao Chenhui
>
> Put all fsl_msi banks in a linked list. The list of banks then can be
> traversed when allocating new msi interrupts.
So there are multiple banks, and you just use the first one that has an
empty slot in it's bitmap?
> S
On Fri, 2010-04-16 at 15:34 +0800, Li Yang wrote:
> From: Zhao Chenhui
>
> In fsl_of_msi_probe(), the virt_msir's chip_data have been stored
> the pointer to struct mpic. We add a struct fsl_msi_cascade_data
> to store the pointer to struct fsl_msi and msir_index. Otherwise,
> the pointer to str
On Fri, 2010-04-16 at 15:34 +0800, Li Yang wrote:
> From: Zhao Chenhui
>
> Make a single PCIe MSI bank shareable through CAMP OSes. The number of
> MSI used by each core can be configured by dts file.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/sysdev/fsl_msi
In message <1271426308.1674.429.ca...@laptop> you wrote:
> On Wed, 2010-04-14 at 14:28 +1000, Michael Neuling wrote:
>
> > > Right, so I suspect this will indeed break some things.
> > >
> > > We initially allowed 0 capacity for when a cpu is consumed by an RT task
> > > and there simply isn't m
On Sun, 18 Apr 2010, Guillaume Knispel wrote:
> Now everything seems to work fine: my device was not previously not
> interrupting anymore after typically 1 or 2 minutes (because the
> interrupt signal stays at level low until the device is served, so
So you are having a level interrupt device and
On Sun, 18 Apr 2010 05:34:39 +0200
Guillaume Knispel wrote:
> From reading the code (kernel/irq stuffs), it seems that at least some
> handle_edge_irq based interrupts are not replayed when enabling if
> desc->chip->retrigger == NULL and on a platform where
> CONFIG_HARDIRQS_SW_RESEND is not set
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