On Fri, Mar 05, 2010 at 08:54:56PM -0700, Grant Likely wrote:
[...]
> The last version of the patches were posted on Feb 8. -rc8 was
> released on Feb 12. For changes to common code, that is a little late
> for getting queued up for the merge window. If it was a subsystem
> that I maintain, say
On Fri, Mar 5, 2010 at 5:28 PM, Anton Vorontsov
wrote:
> On Fri, Mar 05, 2010 at 04:47:06PM -0700, Grant Likely wrote:
> [...]
>> >> I'm not really very comfortable with the whole
>> >> approach being taken. And, while I acked the first patch in the
>> >> series, that patch isn't needed by anythi
On Fri, Mar 05, 2010 at 04:47:06PM -0700, Grant Likely wrote:
[...]
> >> I'm not really very comfortable with the whole
> >> approach being taken. And, while I acked the first patch in the
> >> series, that patch isn't needed by anything except patches 2, 3 & 4.
But you didn't answer my replies,
On Fri, Mar 5, 2010 at 1:35 PM, Andrew Morton wrote:
> On Fri, 5 Mar 2010 13:28:32 -0700
> Grant Likely wrote:
>
>> On Fri, Mar 5, 2010 at 1:00 PM, Andrew Morton
>> wrote:
>> > On Tue, 9 Feb 2010 22:16:20 +0300
>> > Anton Vorontsov wrote:
>> >
>> >> On Tue, Feb 09, 2010 at 10:13:11AM -0700, Gr
powerpc/476: Add dci instruction to async interrupt handlers on DD1 core
From: Dave Kleikamp
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/asm-compat.h |5 +
arch/powerpc/include/asm/cputable.h |1 +
arch/powerpc/kernel/cputable.c| 14 ++
arch/p
powerpc/476: Workaround for DD1.1: Issue lwsync after mtpid
From: Dave Kleikamp
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/asm-compat.h |2 ++
arch/powerpc/kernel/head_44x.S|1 +
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/includ
powerpc/476: Software workaround to fix dcr read/write sequencing.
From: Dave Kleikamp
Copy the register containing the dcr address to a spr before mfdcrx or
mtdcrx instruction. SPRN_SPRG_WSCRATCH_CRIT seems safe enough to use
as a dummy register, as it is only otherwise used by critical interr
powerpc/476: Add isync to the top of all exception handlers for DD1.1 core
From: Dave Kleikamp
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/asm-compat.h |7 ++-
arch/powerpc/kernel/head_booke.h |3 ++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git
powerpc/476: Workaround for dcbf/dcbz workaround on DD1
From: Benjamin Herrenschmidt
On the DD1.1 core, the dcbf and dcbz instructions need to be preceded and
followed by an lwsync. We must trap user-space to ensure that this occurs
there too.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-
powerpc/4xx: Simple platform for the ISS 4xx simulator
From: Torez Smith
This is a trivial 4xx plaform that uses the new simple bsp from
Josh and is handy to use in simulators such as ISS or even Mambo
who don't properly implement most of the actual devices in the
SoC but really only the core.
powerpc/476: define specific cpu table entry DD1.1 core
From: Benjamin Herrenschmidt
There are still some unstable bits in the DD1.1 cores. Don't use
the FPU or the tlbivax operation. Define CPU_FTR_476_DD1_1 for additional
workarounds in later patches.
The DD1 core requires an additional wor
powerpc/47x: defconfig for 476 on the iss 4xx simulator
From: Dave Kleikamp
Signed-off-by: Dave Kleikamp
---
arch/powerpc/configs/44x/iss476-smp_defconfig | 1026 +
1 files changed, 1026 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/configs/44x/iss476-
powerpc/476: Add isync after loading mmu and debug spr's
From: Dave Kleikamp
476 requires an isync after loading MMU and debug related SPR's. Some of
these are in performance-critical paths and may need to be optimized, but
initially, we're playing it safe.
Signed-off-by: Torez Smith
Signed-
powerpc/booke: Add Stack Marking support to Booke Exception Prolog
From: Torez Smith
This patch adds a marker to the exception stack frame to aid in debugging.
It's already inserted on other platforms and xmon recognizes it and
identifies exception frames when showing stack traces.
Signed-off-b
powerpc/476: add machine check handler for 47x core
From: Dave Kleikamp
The 47x core's MCSR varies from 44x, so it needs it's own machine check
handler.
Signed-off-by: Dave Kleikamp
---
arch/powerpc/include/asm/cputable.h |1 +
arch/powerpc/kernel/cputable.c |1 +
arch/powerpc/k
powerpc/47x: Base ppc476 support
From: Dave Kleikamp
This patch adds the base support for the 476 processor. The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.
The goal is to have a single binary that will run on 44x and 47x, but
we s
powerpc/44x: break out cpu init code into stand-alone function
From: Dave Kleikamp
The 47x platform supports multiple cores and shares code with 44x.
Break out code that is common for initializing the primary and secondary
cpus into a function which can be called for both.
Signed-off-by: Dave K
These patches add support for the 476 core. The goal is to have a single
binary that will run on both 44x and 47x, but we still have some details to
work out. The biggest is that the L1 cache line size differs on the two
platforms, but it's currently a compile-time option.
The code was originall
On Fri, Mar 05, 2010 at 11:59:18AM -0800, Andrew Morton wrote:
[...]
> > > /**
> > > * gpiochip_add() - register a gpio_chip
> > > * @chip: the chip to register, with chip->base initialized
> > > @@ -1103,6 +1107,9 @@ fail:
> > >pr_err("gpiochip_add: gpios %d..%d (%s) not registered\n",
> >
On Tue, 9 Feb 2010 10:16:44 -0700
Grant Likely wrote:
> On Fri, Feb 5, 2010 at 1:32 PM, Anton Vorontsov
> wrote:
> > Some platforms (e.g. OpenFirmware) want to know when a particular chip
> > added or removed, so that the platforms could add their specifics for
> > non-platform devices, like I2C
On Wed, Mar 03, 2010 at 11:48:22PM +0530, Vaidyanathan Srinivasan wrote:
> static void __init cpu_init_thread_core_maps(int tpc)
> diff --git a/arch/powerpc/platforms/pseries/Kconfig
> b/arch/powerpc/platforms/pseries/Kconfig
> index c667f0f..b3dd108 100644
> --- a/arch/powerpc/platforms/pseries/
On Fri, 2010-03-05 at 03:15 -0600, Kumar Gala wrote:
> On Mar 4, 2010, at 11:06 AM, Hollis Blanchard wrote:
>
> > On Mon, Mar 1, 2010 at 11:13 AM, Dave Kleikamp
> > wrote:
> > powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
> >
> > From: Benjamin Herrenschmidt
> >
> > The
Heiko Schocher wrote on 2010/03/04 17:30:07:
>
> Hello Joakim,
>
> Joakim Tjernlund wrote:
> > Wolfgang Denk wrote on 2010/03/04 13:16:56:
> >> From: Wolfgang Denk
> >> To: h...@denx.de
> >> Cc: Joakim Tjernlund , Klaus-Jürgen
> >> , linuxppc-...@ozlabs.org, Scott Wood
> >>
> >> Date: 2010/03/0
Hello,
I too facing the same problems. I too have mpc8313 based customized board.
Would you please let me know, if you know how to resolve these messages.
Kindly please acknowledge, thank you
Kind Regards,
Vijay Nikam
On Tue, Mar 2, 2010 at 12:13 AM, Ron Madrid wrote:
> I'm getting a bunch of
This patch adds a gpio driver for MPC512X PowerPCs.
It has been tested on our CAN-CBX-CPU5201 module that
uses a MPC5121 CPU. This platform comes with a couple of
LEDs and configuration switches that have been used for testing.
Signed-off-by: Matthias Fuchs
---
v2: - move driver to arch/powerpc/
>
>
> Got this OOPS a few times after coldstarting out
> board a few times:
>
> Unable to handle kernel paging request for unknown fault
> Faulting instruction address: 0xc020e2b4
> Oops: Kernel access of bad area, sig: 11 [#1]
> TMCUTU
> Modules linked in:
> NIP: c020e2b4 LR: c020e274 CTR: 000
On Mar 4, 2010, at 11:06 AM, Hollis Blanchard wrote:
> On Mon, Mar 1, 2010 at 11:13 AM, Dave Kleikamp
> wrote:
> powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
>
> From: Benjamin Herrenschmidt
>
> There are still some unstable bits on the DD1 and DD1.1 cores. Don't use
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