Re: [patch 1/3] powerpc: Move 64bit VDSO to improve context switch performance

2009-10-03 Thread Benjamin Herrenschmidt
On Sat, 2009-10-03 at 16:51 +0200, Andreas Schwab wrote: > Andreas Schwab writes: > > > Andreas Schwab writes: > > > >> Anton Blanchard writes: > >> > >>> On 64bit applications the VDSO is the only thing in segment 0. Since the > >>> VDSO > >>> is position independent we can remove the hint an

Re: [PATCH] powerpc/5200: make BestComm gen_bd microcode exchangeable

2009-10-03 Thread Albrecht Dreß
Am 03.10.09 16:40 schrieb(en) Wolfram Sang: Sorry, I hardly know anything about the microcode. From what I know, it shouldn't be much fun due to various bugs in the Bestcomm engine. Ummm. That's not encouraging! :-/ Hey! No need for insults! ;) Sorry, that wasn't my intention, but it's a

Re: [patch 1/3] powerpc: Move 64bit VDSO to improve context switch performance

2009-10-03 Thread Andreas Schwab
Andreas Schwab writes: > Andreas Schwab writes: > >> Anton Blanchard writes: >> >>> On 64bit applications the VDSO is the only thing in segment 0. Since the >>> VDSO >>> is position independent we can remove the hint and let get_unmapped_area >>> pick >>> an area. >> >> This breaks gdb. The

Re: [PATCH] powerpc/5200: make BestComm gen_bd microcode exchangeable

2009-10-03 Thread Wolfram Sang
> doesn't give any support, so it's all trial and error and error and > error... If you have any idea, pointers would be appreciated! Sorry, I hardly know anything about the microcode. From what I know, it shouldn't be much fun due to various bugs in the Bestcomm engine. > I don't think so -

Re: [patch 1/3] powerpc: Move 64bit VDSO to improve context switch performance

2009-10-03 Thread Andreas Schwab
Andreas Schwab writes: > Anton Blanchard writes: > >> On 64bit applications the VDSO is the only thing in segment 0. Since the VDSO >> is position independent we can remove the hint and let get_unmapped_area pick >> an area. > > This breaks gdb. The section table in the VDSO image when mapped i

Re: [PATCH] powerpc/5200: make BestComm gen_bd microcode exchangeable

2009-10-03 Thread Albrecht Dreß
Hi Wolfram: Am 03.10.09 11:44 schrieb(en) Wolfram Sang: you wrote your own microcode? :) I modified the bcom_gen_bd_rx_task for a LPB peripheral as to perform Endianess swapping during the transfer (works meanwhile :-). Modifying the standard kernel code for testing seemed to be the wron

Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite

2009-10-03 Thread Joakim Tjernlund
Benjamin Herrenschmidt wrote on 03/10/2009 12:57:28: > On Sat, 2009-10-03 at 11:24 +0200, Joakim Tjernlund wrote: > > > > So yes, there is a missing _tlbil_va() missing for 8xx somewhere > > but there is something more too. > > Maybe your new filter functions and my > > powerpc, 8xx: DTLB Erro

Re: [PATCH] powerpc: fix segment mapping in vdso32

2009-10-03 Thread Benjamin Herrenschmidt
On Sat, 2009-10-03 at 11:25 +0200, Andreas Schwab wrote: > Due to missing segment assignments the .text section was put in the NOTES > segment (and marked as NOTE section), and the .got was put in the DYNAMIC > segment. Ouch, good catch ! Thanks. Cheers, Ben. > Signed-off-by: Andreas Schwab > -

Re: Is volatile always verboten for FSL QE structures?

2009-10-03 Thread Benjamin Herrenschmidt
> Making the target of foo volatile properly rechecks the condition on > each iteration. > > OTOH my PPC box runs fine, so I'm probably missing something obvious. Probably because the IO accessors do -both- volatile casts and add the barriers :-) Ben.

Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite

2009-10-03 Thread Benjamin Herrenschmidt
On Sat, 2009-10-03 at 11:24 +0200, Joakim Tjernlund wrote: > > So yes, there is a missing _tlbil_va() missing for 8xx somewhere > but there is something more too. > Maybe your new filter functions and my > powerpc, 8xx: DTLB Error must check for more errors. > will do the trick? Well, if we can'

Re: Is volatile always verboten for FSL QE structures?

2009-10-03 Thread Simon Richter
Hi, > > >> 'volatile' just doesn't really do what you think it should do. The > > >> PowerPC architecture is too complicated w.r.t. ordering of reads and > > >> writes. In other words, you can't trust it. It's not sufficient on PowerPC. It might be necessary, depending on the compiler's mood f

Re: [PATCH] powerpc/5200: make BestComm gen_bd microcode exchangeable

2009-10-03 Thread Wolfram Sang
Hi Albrecht, you wrote your own microcode? :) approach looks ok to me in general, but this patch is line-wrapped. On Thu, Oct 01, 2009 at 09:55:38PM +0200, Albrecht Dreß wrote: > This patch adds a method for defining different microcodes than the > pe-defined ones for the MPC52xx processor's Be

Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite

2009-10-03 Thread Joakim Tjernlund
Benjamin Herrenschmidt wrote on 03/10/2009 10:31:18: > > On Sat, 2009-10-03 at 10:05 +0200, Joakim Tjernlund wrote: > > Cannot shake the feeling that it this snip of code that causes it > > lwz r11, 0(r10) /* Get the level 1 entry */ > > rlwinm. r10, r11,0,0,19 /* Extract p

[PATCH] powerpc: fix segment mapping in vdso32

2009-10-03 Thread Andreas Schwab
Due to missing segment assignments the .text section was put in the NOTES segment (and marked as NOTE section), and the .got was put in the DYNAMIC segment. Signed-off-by: Andreas Schwab --- arch/powerpc/kernel/vdso32/vdso32.lds.S |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) di

Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite

2009-10-03 Thread Benjamin Herrenschmidt
On Sat, 2009-10-03 at 10:05 +0200, Joakim Tjernlund wrote: > Cannot shake the feeling that it this snip of code that causes it > lwz r11, 0(r10) /* Get the level 1 entry */ > rlwinm. r10, r11,0,0,19 /* Extract page descriptor page > address */ > beq 2f

Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite

2009-10-03 Thread Joakim Tjernlund
Scott Wood wrote on 02/10/2009 23:49:49: > > On Thu, Oct 01, 2009 at 08:35:59AM +1000, Benjamin Herrenschmidt wrote: > > >From what I can see, the TLB miss code will check _PAGE_PRESENT, and > > when not set, it will -still- insert something into the TLB (unlike > > all other CPU types that go str