Hello Felix,
On Thu, Sep 17, 2009 at 6:17 AM, Felix Radensky wrote:
> On my custom MPC8536 based board running 2.6.31 kernel
> FPGA is connected via x2 PCI-E lane. FPGA is identified
> during PCI scan and is visible via lspci.
>
I committed a PCI Express device driver for an Altera FPGA (chainin
This patch creates the dts files for each core and splits the devices between
the two cores for P2020RDB.
core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto, global-util, pci0
core1 has L2, dma2, eth0, pci1, msi.
MPIC is shared between two cores but each core will protect its
interrupt
Hi, Benjamin
Benjamin Herrenschmidt wrote:
However when I attempt to access FPGA memory my mmapping it in
userspace the read hangs. The same happens in kernel space. Does it
happen because FPGA memory is marked as disabled, or because FPGA
code is doing something wrong ?
Can you access the
Sachin Sant wrote:
Tejun Heo wrote:
Ah... sorry about that. Sachin, is it possible for you to build the
kernel with debug info and ask gdb where the stalling NIP is in the c
file?
<6>NET: Registered protocol family 10
<3>BUG: soft lockup - CPU#2 stuck for 61s! [modprobe:1865]
<4>Modules lin
