On Wed, Jul 08, 2009 at 10:52:59PM -0500, Kumar Gala wrote:
> To further verify this if I switch the -me500 to -mspe and build things
> seem to be ok. This further points at some APU section related bug.
Like omitting .PPC.EMB.apuinfo from your kernel link script? See the
ld info doc on orphan
On Jul 8, 2009, at 10:39 PM, Kumar Gala wrote:
On Jul 8, 2009, at 6:39 PM, Alan Modra wrote:
On Wed, Jul 08, 2009 at 05:41:39PM -0500, Kumar Gala wrote:
If we modify the linker script:
_end2 = .;
_end3 = ALIGN(4096);
_end4 = ALIGN(PAGE_SIZE);
. = ALIGN(PAGE_SIZE);
_end
On Jul 8, 2009, at 6:39 PM, Alan Modra wrote:
On Wed, Jul 08, 2009 at 05:41:39PM -0500, Kumar Gala wrote:
If we modify the linker script:
_end2 = .;
_end3 = ALIGN(4096);
_end4 = ALIGN(PAGE_SIZE);
. = ALIGN(PAGE_SIZE);
_end = . ;
PROVIDE32 (end = .);
and the resu
On Jul 8, 2009, at 6:39 PM, Alan Modra wrote:
On Wed, Jul 08, 2009 at 05:41:39PM -0500, Kumar Gala wrote:
If we modify the linker script:
_end2 = .;
_end3 = ALIGN(4096);
_end4 = ALIGN(PAGE_SIZE);
. = ALIGN(PAGE_SIZE);
_end = . ;
PROVIDE32 (end = .);
and the resu
On Wed, Jul 08, 2009 at 06:46:18PM -0500, Dave Kleikamp wrote:
>On booke processors, gdb is seeing spurious SIGTRAPs when setting a
>watchpoint.
>
>user_disable_single_step() simply quits when the DAC is non-zero. It should
>be clearing the DBCR0_IC and DBCR0_BT bits from the dbcr0 register and
>T
On booke processors, gdb is seeing spurious SIGTRAPs when setting a
watchpoint.
user_disable_single_step() simply quits when the DAC is non-zero. It should
be clearing the DBCR0_IC and DBCR0_BT bits from the dbcr0 register and
TIF_SINGLESTEP from the thread flag.
Signed-off-by: Dave Kleikamp
d
On Wed, Jul 08, 2009 at 05:41:39PM -0500, Kumar Gala wrote:
> If we modify the linker script:
>
> _end2 = .;
> _end3 = ALIGN(4096);
> _end4 = ALIGN(PAGE_SIZE);
> . = ALIGN(PAGE_SIZE);
> _end = . ;
> PROVIDE32 (end = .);
>
> and the result is:
>
> 1000 A _end
> I was hoping to convert this working initrd to initramfs before I try
> and create my own initrd, I'm still learning about this process. I got
> this to work yesterday morning, but I'm not sure what changed or what
> I'm doing differently...
> Can somebody help me figure out what's missing?
Neve
Alan,
We are seeing an issue w/ld and kernel linking of 32-bit kernels.
The ld from fedora 11 (2.19.51.0.2-17.fc11 20090204) ends not
providing the proper address for _end.
Building stock v2.6.30 w/the mpc85xx_defconfig we get:
1000 A _end
Using 2.18.50.20080215 we get:
c068 A _en
looks good, applied
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On Jul 8, 2009, at 2:33 PM, Ira W. Snyder wrote:
On Wed, Jul 08, 2009 at 01:09:39PM -0500, Kumar Gala wrote:
On Jul 8, 2009, at 11:19 AM, Ira W. Snyder wrote:
Add support for the Freescale MPC83xx memory controller to the
existing
driver for the Freescale MPC85xx memory controller. The only
Hello, I have a working system with an initrd ramdisk and I'm having
some trouble switching it over to initramfs.
This is for an EP88xc Embedded Planet board, now running U-Boot and
using kernel 2.6.29. I prepare my initrd using:
genext2fs -U -d rootfs -D rootfs_devices.tab -b 9700 -i 380 initrd.
On Wed, Jul 08, 2009 at 01:09:39PM -0500, Kumar Gala wrote:
>
> On Jul 8, 2009, at 11:19 AM, Ira W. Snyder wrote:
>
>> Add support for the Freescale MPC83xx memory controller to the
>> existing
>> driver for the Freescale MPC85xx memory controller. The only
>> difference
>> between the two proc
On Jul 8, 2009, at 11:19 AM, Ira W. Snyder wrote:
Add support for the Freescale MPC83xx memory controller to the
existing
driver for the Freescale MPC85xx memory controller. The only
difference
between the two processors are in the CS_BNDS register parsing code.
The L2 cache controller doe
Acked-by: Dave Jiang
On 07/08/2009 09:15 AM, Ira W. Snyder wrote:
When building without CONFIG_PCI the edac_pci_idx variable is unused,
causing a build-time warning. Wrap the variable in #ifdef CONFIG_PCI, just
like the rest of the PCI support.
Signed-off-by: Ira W. Snyder
---
drivers/edac/m
Add support for the Freescale MPC83xx memory controller to the existing
driver for the Freescale MPC85xx memory controller. The only difference
between the two processors are in the CS_BNDS register parsing code.
The L2 cache controller does not exist on the MPC83xx, but the OF subsystem
will not
When building without CONFIG_PCI the edac_pci_idx variable is unused,
causing a build-time warning. Wrap the variable in #ifdef CONFIG_PCI, just
like the rest of the PCI support.
Signed-off-by: Ira W. Snyder
---
drivers/edac/mpc85xx_edac.c |2 ++
1 files changed, 2 insertions(+), 0 deletions
At Fri, 26 Jun 2009 15:14:54 +0200,
Gerhard Pircher wrote:
>
>
> Original-Nachricht
> > Datum: Wed, 24 Jun 2009 11:47:13 +0200
> > Von: Takashi Iwai
> > An: "Gerhard Pircher"
> > CC: b...@kernel.crashing.org, linuxppc-...@ozlabs.org
> > Betreff: Re: ALSA fixes for non-coherent
At Wed, 08 Jul 2009 13:01:50 +1000,
Benjamin Herrenschmidt wrote:
>
> On Mon, 2009-06-22 at 08:34 +1000, Benjamin Herrenschmidt wrote:
> > On Sun, 2009-06-21 at 20:18 +0200, Gerhard Pircher wrote:
> > > Hi,
> > >
> > > Takashi Iwai posted patches to make ALSA work on non-coherent PPC32
> > > syst
It now works, in the dts
interrupt-controller = < &gpt6 >; // Use GPT6 as
should have been
interrupt-parent = < &gpt6 >; // Use GPT6 as
On Tue, Jul 7, 2009 at 5:57 PM, Grant Likely wrote:
> On Tue, Jul 7, 2009 at 8:31 AM, Henk Stegeman wrote:
>> I tried to make use of the irq-controller
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