Hello,
I wanted algorithm for creating hash tables used in paging mechanism..
In the manual that i read i got algorithm to convert Effective Address
to Real Address using these hash tables that are created..but i could
not find how these hash tables are created in first place using the
Real addres
Change the PS3 platform code to use hard coded numbers for its
LV1 device types.
The PS3 platform code was incorrectly using some scsi block
constants for the device type returned from the LV1 hypervisor.
Fixes build errors like these when CONFIG_BLOCK=n:
In file included from include/scsi/scs
This adds support for an EDAC memory controller adaptation driver for
the "ibm,sdram-4xx-ddr2" ECC controller realized in the AMCC PowerPC
405EX[r].
Signed-off-by: Grant Erickson
---
At present, this driver has been developed and tested against the
controller realization in the AMCC PPC405EX[r] o
Hi Andre,
I started the development with 2.6.28. Thanks for all of your
suggestions but I managed to find the solution today. The problem was
that the PCI-cards did not have class specified. Adding a fixup hook
to the cards in quirks.c resolved the issue.
On Fri, Feb 6, 2009 at 14:34, Andre Schwa
On Fri, 06 Feb 2009 11:40:41 -0800
Grant Erickson wrote:
> On 1/30/09 2:05 PM, Andrew Morton wrote:
> > On Fri, 30 Jan 2009 09:54:42 -0700 dougthomp...@xmission.com wrote:
> >> From: Grant Erickson
> >
> > Perhaps a powerpc mailing list should have been cc'ed?
>
> The first round patch went to
On 1/30/09 2:05 PM, Andrew Morton wrote:
> On Fri, 30 Jan 2009 09:54:42 -0700 dougthomp...@xmission.com wrote:
>> From: Grant Erickson
>
> Perhaps a powerpc mailing list should have been cc'ed?
The first round patch went to Doug, the BlueSmoke (EDAC) mailing list and
the Linux/PowerPC mailing li
Dear David,
In message <200902060824.06851.david.jan...@protonic.nl> you wrote:
>
> I decided to try out Application Note AN3793 from Freescale (3D Graphics on
> the ADS512101 Board Using OpenGL ES).
>
> I started trying to load the provided (binary!) kernel modules into our
> kernel, but I am
On Thu, 2009-02-05 at 15:58 -0500, Josh Boyer wrote:
> On Fri, Feb 06, 2009 at 07:56:22AM +1100, Benjamin Herrenschmidt wrote:
> >
> >> Which begs the question of what master is for. So far, it's just been
> >> a mirror of next from what I can tell. Maybe it should just track
> >> Linus' tree?
>
This patch adds a new driver: sdhci-of. The driver is similar to
the sdhci-pci, it contains common probe code, and controller-specific
ops and quirks.
So far there are only Freescale eSDHC ops and quirks.
Signed-off-by: Anton Vorontsov
Acked-by: Arnd Bergmann
---
drivers/mmc/host/Kconfig|
This patch adds SDHCI_QUIRK_FSL quirk. The quirk is used to instruct
the sdhci driver about various FSL eSDHC host incompatibilities:
1) FSL eSDHC controllers can support maximum block size up to 4096
bytes. The MBL (Maximum Block Length) field in the capabilities
register extended by one bi
FSL eSDHC hosts don't provide clocks bits in the capabilities register,
instead we're getting clocks values from the device tree.
There is somewhat similar change[1] from Ben Dooks, the change adds
callbacks for getting the clocks. But for eSDHC the callbacks are
superfluous, since the clocks are
FSL eSDHC hosts have incompatible register map to manage the SDCLK.
This patch adds set_clock callback so that drivers could overwrite
set_clock behaviour.
Similar patch[1] was posted by Ben Dooks, though in Ben's version the
callback is named change_clock, plus the patch has some unrelated bits
t
Some hosts (that is, FSL eSDHC) throw PIO interrupts during DMA
transfers, this causes tons of unneeded interrupts, and thus highly
degraded speed.
This patch adds SDHCI_QUIRK_PIO_IRQS_DURING_DMA quirk. When specified,
the sdhci driver will disable PIO interrupts during DMA transfers.
Signed-off-
SDHCI driver must take special care when working with "triggering"
registers on hosts with strict 32 bit addressing.
In FSL eSDHC hosts all registers are 32 bit width, writing to the
first half of any register will cause [undefined?] write the second
half of the register. That is, 16 bit write to
This patch adds SDHCI_QUIRK_INVERTED_WRITE_PROTECT quirk. When
specified, the sdhci driver will invert WP state.
p.s. Actually, the quirk is more board-specific than
controller-specific.
Signed-off-by: Anton Vorontsov
---
drivers/mmc/host/sdhci.c |2 ++
drivers/mmc/host/sdhci.h |2
This patch adds SDHCI_QUIRK_BROKEN_CARD_DETECTION quirk. When specified,
sdhci driver will set MMC_CAP_NEEDS_POLL MMC host capability, and won't
enable card insert/remove interrupts.
This is needed for hosts with unreliable card detection, such as FSL
eSDHC. The original eSDHC driver was tring to
A new restricted integer type introduced: sdhci_reg_t.
Header file now specifies registers via sdhci_reg() inline function.
Only one place (not counting sdhci_def_*() accessors) need to cast
a register back to an offset, i.e. sdhci_finish_command().
>From now on sparse tool will warn about IO mem
Currently the SDHCI driver works with PCI accessors (write{l,b,w} and
read{l,b,w}).
With this patch drivers may change memory accessors, so that we can
support hosts with "weird" IO memory access requirments.
For example, in "FSL eSDHC" SDHCI hardware all registers are 32 bit
width, with big-endi
From: Ben Dooks
The Samsung SDHCI (and FSL eSDHC) controller block seems to fail
to generate an INT_DATA_END after the transfer has completed and
the bus busy state finished.
Changes in e809517f6fa5803a5a1cd56026f0e2190fc13d5c to use the
new busy method are the cause of the behaviour change.
Si
Hi all,
There were only a few comments on the previous version. So, here is
the second call for comments.
Changes since the first RFC:
- Use of_iomap() in sdhci-of.c (suggested by Arnd Bergmann). Also added
Arnd's Acked-by: line for the sdhci-of patch.
- Kconfig help text improved (thanks to M
2.6.29-rc3-git9 randconfig build fails with
CALLarch/powerpc/kernel/prom_init_check.sh
CC arch/powerpc/platforms/ps3/setup.o
In file included from include/scsi/scsi.h:12,
from arch/powerpc/platforms/ps3/platform.h:25,
from arch/powerpc/platforms/ps3/setu
On Feb 3, 2009, at 10:07 PM, Benjamin Herrenschmidt wrote:
--- work.git.orig/arch/powerpc/platforms/powermac/setup.c-static void
pmac_cpu_die(void)
+static void pmac64_cpu_die(void)
...
--- work.git.orig/arch/powerpc/platforms/powermac/smp.c 2009-01-05
02:09:08.0 -0600
-void cpu_die(
Please pull from 'merge' branch of
master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc.git merge
to receive the following updates:
arch/powerpc/boot/dts/mpc8313erdb.dts | 11 ---
arch/powerpc/configs/83xx/mpc8313_rdb_defconfig |2 +-
arch/powerpc/platforms/
On Feb 5, 2009, at 1:04 PM, Anton Vorontsov wrote:
Simply add appropriate sdhci nodes.
Note that U-Boot should configure pin multiplexing for eSDHC prior
to Linux could use it. U-Boot should also fill-in the clock-frequency
property (eSDHC clock depends on board-specific SCCR[ESDHCCM] bits).
On Feb 5, 2009, at 1:04 PM, Anton Vorontsov wrote:
- sdhc node renamed to sdhci ("sdhc" name is confusing since SDHC is
used to name Secure Digital High Capacity cards, while SDHCI is an
interface).
- Get rid of "fsl,esdhc" compatible entry, it's replaced by the
"fsl,-esdhc" scheme;
- Get
On Feb 5, 2009, at 1:04 PM, Anton Vorontsov wrote:
This patch documents OF bindings for the Freescale Enhanced Secure
Digital Host Controller.
Signed-off-by: Anton Vorontsov
---
Documentation/powerpc/dts-bindings/fsl/esdhc.txt | 24 +
+
1 files changed, 24 insertions(+)
On Feb 4, 2009, at 12:48 PM, Benjamin Walsh wrote:
Hi Milton,
I've tracked it down to the device tree passed to the second kernel
being screwed-up when patched by kexec-tools. Namely, it was creating
linux,usable-memory entries that were wrong, and the MMU
initialization hung when it failed
On Jan 27, 2009, at 2:44 AM, paulfax wrote:
This is a simple change to correct problems when using set_irq_type
on platforms using CPM2.
This code correct the problem on most platform but still fails on
8272 derived platforms for some interrupts.
On 8272 PC2 & 3 are missing and PC 23 & 29 ar
On Feb 4, 2009, at 3:43 PM, Julia Lawall wrote:
From: Julia Lawall
Taking sizeof the result of sizeof is quite strange and does not
seem to be
what is wanted here.
This was fixed using the following semantic patch.
(http://www.emn.fr/x-info/coccinelle/)
//
@@
expression E;
@@
- sizeof
On Feb 5, 2009, at 2:10 PM, Anton Vorontsov wrote:
TSEC0 is connected to Vitesse 7385 5-port switch. The switch
isn't connected to any mdio bus, the link to the switch is fixed
to Full-duplex 1000 Mb/s (no pause).
This patch fixes following failure during bootup:
m...@24520:01 not found
eth0:
On Feb 5, 2009, at 2:10 PM, Anton Vorontsov wrote:
commit b31a1d8b41513b96e9c7ec2f68c5734cef0b26a4 ("gianfar: Convert
gianfar to an of_platform_driver") introduced a child node for
the ether...@25000 controller, but no address and size cells
specifiers were added, and that makes dtc unhappy:
D
On Feb 5, 2009, at 6:10 PM, Michael Neuling wrote:
I noticed this doing some randconfig testing (.config below). I have
CONFIG_PM but no CONFIG_SUSPEND. Bug is against mainline.
arch/powerpc/sysdev/built-in.o: In function `ipic_suspend':
ipic.c:(.text+0x6b34): undefined reference to `fsl_dee
On Feb 6, 2009, at 10:04 AM, Scott Wood wrote:
On Fri, Feb 06, 2009 at 11:10:27AM +1100, Michael Neuling wrote:
I noticed this doing some randconfig testing (.config below). I have
CONFIG_PM but no CONFIG_SUSPEND. Bug is against mainline.
arch/powerpc/sysdev/built-in.o: In function `ipic_su
On Fri, Feb 06, 2009 at 11:10:27AM +1100, Michael Neuling wrote:
> I noticed this doing some randconfig testing (.config below). I have
> CONFIG_PM but no CONFIG_SUSPEND. Bug is against mainline.
>
> arch/powerpc/sysdev/built-in.o: In function `ipic_suspend':
> ipic.c:(.text+0x6b34): undefined
On Thu, Feb 05, 2009 at 08:52:56PM -0600, Kumar Gala wrote:
> On Feb 5, 2009, at 1:04 PM, Anton Vorontsov wrote:
>> On Thu, Jan 22, 2009 at 01:15:01PM -0600, Kumar Gala wrote:
>>> On Jan 21, 2009, at 8:00 PM, Anton Vorontsov wrote:
This patch adds a new driver: sdhci-of. The driver is similar
The i2c_wait() function is using wait_event_interruptible_timeout() to wait for
the I2C controller to signal that it has completed an I2C bus operation. If
the process that causes the I2C operation terminated abruptly, the wait will
be interrupted, returning an error. It is better to let the I2C
Tobias,
are you starting with 2.6.28 or are you upgrading ?
My system runs very fine with 2.6.27
Tobias Knutsson wrote:
I am currently trying to get an MPC5200-based board to run Linux
2.6.28. Most of the devices are working, however i have some issues
with the PCI-bus. More precisely, the
I have now found drivers/pci/quirks.c which seems to be the place for
these types of things. However, since this code is unlikely to ever
make it to mainline, is it possible to register a fixup hook in a
platform setup file (lite5200.c and friends)?
On Fri, Feb 6, 2009 at 12:46, Tobias Knutsson
Currently emulate_step() emulates mr. instructions without updating cr0
and this can be disastrous. Don't emulate mr.
This bug has been around for a while, but I am not sure if its a worthy
-stable candidate. I'll leave it to Ben do decide.
Signed-off-by: Ananth N Mavinakayanahalli
---
arch/pow
Hi David
I'm also run on a custom board, and using the MBX.
You need to get the device tree file right. You will see the MBX reserved
the irq 66 in the boot printout.
Instead of using insmod use modprobe. The are 2 versions of rc.pvr.
Best Regard
Klaus Pedersen
I a early thread about memcpy f
Ok, I have had a breakthrough. I was trying to find out where the
resources were supposed to be allocated and that was when i found this
section of code in pbus_assign_resources_sorted() in
drivers/pci/setup-bus.c:
/* Don't touch classless devices or host bridges or ioapics. */
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