On Sat, Nov 01, 2008 at 11:47:58AM -0500, Kumar Gala wrote:
>
> On Nov 1, 2008, at 7:33 AM, Nick Piggin wrote:
>
> >A previous change removed __SUBARCH_HAS_LWSYNC define, and replaced it
> >with __powerpc64__. smp_wmb() seems to be the last place not updated.
>
> Uugh... no.. I missed the patch
On Sat, 2008-11-01 at 07:30 -0400, Josh Boyer wrote:
>
> That is on purpose. The chip has an errata that causes badness if
> you use the last XX bytes of DRAM. I forget exactly what XX is, but
> we just remove the last page.
Doing that from the device-tree is very hairy tho... you end up with
i
On Arches, SGMII0 Rx/Tx on CPU0 is wired to SGMII0 Tx/Rx on CPU1.
Add GPCS as a phy type to allow for this.
Signed-off-by: Victor Gallardo <[EMAIL PROTECTED]>
---
arch/powerpc/boot/dts/arches.dts |3 ++-
drivers/net/ibm_newemac/core.c |5 -
drivers/net/ibm_newemac/phy.c| 29 ++
* David Gibson | 2008-10-14 13:00:04 [+1100]:
>Oh, one other thing. Since we are now unconditionally copying the dtb
>into a malloc()ed buffer, possibly it would be sensible to add a
>little padding to the buffer at that point, so that further device
>tree manipulations won't need to reallocate i
On Nov 1, 2008, at 7:33 AM, Nick Piggin wrote:
A previous change removed __SUBARCH_HAS_LWSYNC define, and replaced it
with __powerpc64__. smp_wmb() seems to be the last place not updated.
Uugh... no.. I missed the patch that removed __SUBARCH_HAS_LWSYNC, but
thats no good. We have LWSYNC o
Anton. Thanks for the info you provide.
The code I have actually works fine on MPC8568. It does NOT work on MPC8360.
The value of following register are correct based on the manual. And
the RxBD flag changed as well. I shall see the bit of UCCE changes,
Right? Do I miss provision anything? Is the
Hi guys,
This is an interesting one for me. AFAIKS it is possible to use lwsync for
a full barrier after a successful ll/sc operation, right? (or stop me here
if I'm wrong).
Anyway, I was interested in exploring this. Unfortunately my G5 might not
be very indicative of more modern, and future dev
smp_rmb can be lwsync if possible. Clarify the comment.
Signed-off-by: Nick Piggin <[EMAIL PROTECTED]>
---
Index: linux-2.6/arch/powerpc/include/asm/system.h
===
--- linux-2.6.orig/arch/powerpc/include/asm/system.h2008-11-01
23:5
A previous change removed __SUBARCH_HAS_LWSYNC define, and replaced it
with __powerpc64__. smp_wmb() seems to be the last place not updated.
Signed-off-by: Nick Piggin <[EMAIL PROTECTED]>
---
Index: linux-2.6/arch/powerpc/include/asm/system.h
===
On Fri, Oct 31, 2008 at 06:23:28PM -0500, Hollis Blanchard wrote:
>On Wed, Oct 22, 2008 at 9:28 AM, Christian Ehrhardt
><[EMAIL PROTECTED]> wrote:
>> Hi Ilya,
>> I just tried your patch on my 440 board because it would help us in our
>> environment.
>> Unfortunately I run into a bug on early boot (
On my screen, when something crashes, I only have space for maybe
16 functions of the stack trace before the information above it
scrolls off the screen. It's easy to hack the kernel to print out
only that much, but it's harder to remember to do it. This patch
introduces a config option for it so t
2008/11/1 Simon Horman <[EMAIL PROTECTED]>
> On Fri, Oct 31, 2008 at 09:53:23AM +0300, Maxim Uvarov wrote:
> > 2008/10/31 Simon Horman <[EMAIL PROTECTED]>
> >
> > > Hi,
> > >
> > > Could someone please comment on the satus of this patch?
> > >
> > Hello, Simon
> >
> > I can not reproduce error w
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