> What does this all mean to my GigE (dual 1.1 GHz 7455s)? Is this
> thing supposed to be able to spread irq between its cpus?
Depends on the interrupt controller. I don't know that machine
but for example the Apple Dual G5's use an MPIC that can spread
based on an internal HW round robin scheme.
On Sat, 2008-10-25 at 21:04 -0700, David Miller wrote:
> But back to my original wonder, since I've always tipped off of this
> generic IRQ layer cpu mask, when was it ever defaulting to zero
> and causing the behvaior your powerpc guys actually want? :-)
Well, I'm not sure what Kumar wants. Most
This adds a SPI driver for the SPI controller found in the IBM/AMCC
4xx PowerPC's.
Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
Signed-off-by: Wolfgang Ocker <[EMAIL PROTECTED]>
---
Changes in v3:
- When the device is removed the GPIOs are released. The memory
for the GPIO array is freed.
Ch
From: Kevin Diggs <[EMAIL PROTECTED]>
Date: Sat, 25 Oct 2008 15:53:46 -0700
> What does this all mean to my GigE (dual 1.1 GHz 7455s)? Is this
> thing supposed to be able to spread irq between its cpus?
Networking interrupts should lock onto a single CPU, unconditionally.
That's the optimal way t
From: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Date: Sun, 26 Oct 2008 08:33:09 +1100
> Well, I don't know how you do it but on powerpc, we explicitely fill the
> affinity masks at boot time when we can spread interrupts... Maybe we
> should change it the other way around and limit the mask when
Benjamin Herrenschmidt wrote:
On Fri, 2008-10-24 at 16:18 -0700, David Miller wrote:
From: Kumar Gala <[EMAIL PROTECTED]>
Date: Fri, 24 Oct 2008 10:57:38 -0500
Commit 18404756765c713a0be4eb1082920c04822ce588 introduced a regression
on a subset of SMP based PPC systems whose interrupt control
On Fri, 2008-10-24 at 16:18 -0700, David Miller wrote:
> From: Kumar Gala <[EMAIL PROTECTED]>
> Date: Fri, 24 Oct 2008 10:57:38 -0500
>
> > Commit 18404756765c713a0be4eb1082920c04822ce588 introduced a regression
> > on a subset of SMP based PPC systems whose interrupt controller only
> > allow set
On Saturday 25 October 2008, Wolfgang Ocker wrote:
> > >> This adds a SPI driver for the SPI controller found in the IBM/AMCC
> > >> 4xx PowerPC's.
> > >>
> > >> Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
> > >
> > >Signed-off-by: Wolfgang Ocker <[EMAIL PROTECTED]>
> >
> > Unless you actually
On Sat, 2008-10-25 at 07:39 -0400, Josh Boyer wrote:
> On Sat, Oct 25, 2008 at 12:11:29PM +0200, Wolfgang Ocker wrote:
> >On Sat, 2008-10-25 at 06:30 +0200, Stefan Roese wrote:
> >> This adds a SPI driver for the SPI controller found in the IBM/AMCC
> >> 4xx PowerPC's.
> >>
> >> Signed-off-by: St
On Sat, Oct 25, 2008 at 12:11:29PM +0200, Wolfgang Ocker wrote:
>On Sat, 2008-10-25 at 06:30 +0200, Stefan Roese wrote:
>> This adds a SPI driver for the SPI controller found in the IBM/AMCC
>> 4xx PowerPC's.
>>
>> Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
>
>Signed-off-by: Wolfgang Ocker <[
On Sat, 2008-10-25 at 06:30 +0200, Stefan Roese wrote:
> This adds a SPI driver for the SPI controller found in the IBM/AMCC
> 4xx PowerPC's.
>
> Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
Signed-off-by: Wolfgang Ocker <[EMAIL PROTECTED]>
___
Lin
On Sat, Oct 25, 2008 at 12:07:06AM -0600, Grant Likely wrote:
> On Fri, Oct 24, 2008 at 3:41 PM, Anton Vorontsov
> <[EMAIL PROTECTED]> wrote:
> > On Fri, Oct 24, 2008 at 12:59:00PM -0700, John Linn wrote:
> >> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> >> index 7f2ee27..f6b0da8 1006
From: "Chris Friesen" <[EMAIL PROTECTED]>
Date: Fri, 24 Oct 2008 23:42:48 -0600
> David Miller wrote:
> > From: "Chris Friesen" <[EMAIL PROTECTED]>
> > Date: Fri, 24 Oct 2008 17:39:00 -0600
> >
> >> So...it would appear that the NAPI code is somehow buggy, and
> >> 6ba33ac should probably be reve
13 matches
Mail list logo
