Hi,
On Fri, Aug 22, 2014 at 4:19 PM, Andreas Färber wrote:
> Hi,
>
> s/Caibrate/Calibrate/
Sure, will rectify the title, thanks for pointing it out.
--
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India
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To unsubscribe from this list: send the line "uns
Hi Jingoo,
On Wed, Aug 27, 2014 at 7:28 AM, Jingoo Han wrote:
> On Thursday, August 21, 2014 11:55 PM, Vivek Gautam wrote:
>>
>> Adding phy calibrate callback, which facilitates setting certain
>> PHY settings post initialization of the PHY controller.
>> Exynos5420 a
This USB 3.0 PHY controller is also present on Exynos7
platform, so adding the dependency on ARCH_EXYNOS7 for this driver.
Signed-off-by: Vivek Gautam
---
drivers/phy/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/dwc3-exynos.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b
Some Exynos SoCs have a separate regulator controlling a
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
vbus supply on the port.
Signed-off-by: Vivek Gautam
---
drivers/phy/phy-exynos5-usbdrd.c | 27 +--
1
The Exynos-DWC3 USB 3.0 DRD controller is also present on
Exynos7 platform, so adding the dependency on ARCH_EXYNOS7
for this driver.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/Kconfig b
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
So get the same and control in the phy-exynos5-usbdrd driver.
Signed-off-by: Vivek Gautam
---
.../devicetree/bindings/phy/samsung-phy.txt|4
drivers/phy/phy-exynos5-usbdrd.c
.html
The series is based on usb-next branch.
Vivek Gautam (5):
usb: dwc3: exynos: Add support for SCLK present on Exynos7
phy: exynos5-usbdrd: Add pipe-clk and utmi-clk support
phy: exynos5-usbdrd: Add facility for VBUS-BOOST-5V supply
usb: dwc3: Adding Kconfig dependency for Exynos7
phy
> Signed-off-by: Jaewon Kim
> Tested-by: Chanwoo Choi
> ---
Patch looks good to me.
Reviewed-by: Vivek Gautam
> .../devicetree/bindings/phy/samsung-phy.txt|3 ++-
> drivers/phy/phy-exynos5-usbdrd.c | 10 ++
> include/linux/mfd/syscon/exynos5-
hcd->rsrc_len = resource_size(res);
>>
>> /*
>>* OTG driver takes care of PHY initialization, clock management,
>> --
>> 1.9.1
>>
>>
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>
egisters.
Cc: Vivek Gautam
Since ehci-msm and msm_otg both want to control few USB registers,
it makes sense to request ioremap'ed region in both drivers.
Acked-by: Vivek Gautam
I can see a patch in mailing list for adding both ehci-host and otg on msm
[1].
But I think it has not yet m
Hi,
--
From: "Alan Stern"
Sent: Monday, April 27, 2015 8:14 PM
To: "Ivan T. Ivanov"
Cc: "Greg Kroah-Hartman" ;
; ;
; "Vivek Gautam"
Subject: Re: [PATCH v2] Revert "usb: host: ehci-msm: Use
devm_io
rs.
So ensuring now that the controller driver requests the necessary
VDD regulators (if available, unless there are direct VDD rails),
and enable them so as to make them working.
Signed-off-by: Vivek Gautam
Signed-off-by: Anand Moon
Cc: Jingoo Han
Cc: Alan Stern
---
Initial version of this pa
--
From: "Krzysztof Kozlowski"
Sent: Monday, June 08, 2015 7:40 AM
To: "Anand Moon" ; "Rob Herring"
; "Pawel Moll" ; "Mark Rutland"
; "Ian Campbell" ;
"Kumar Gala"
Hi,
On Monday, June 08, 2015 3:50 PM, "Anand Moon"
On 8 June 2015 at 10:58, Vivek Gautam wrote:
Hi,
On Monday, June 08, 2015 10:44 AM, "Krzysztof Kozlowski"
wrote:
my apologies for being late in replying to this thread.
2015-06-08 13:21 GMT+09:00 Anand Moon :
.
So ensuring now that the controller driver requests the necessary
VDD regulators (if available, unless there are direct VDD rails),
and enable them so as to make them working on exynos systems.
Signed-off-by: Vivek Gautam
Cc: Jingoo Han
Cc: Krzysztof Kozlowski
Cc: Alan Stern
---
These patche
.
So ensuring now that the controller driver requests the necessary
VDD regulators (if available, unless there are direct VDD rails),
and enable them so as to make them working on exynos systems.
Signed-off-by: Vivek Gautam
Cc: Jingoo Han
Cc: Krzysztof Kozlowski
Cc: Alan Stern
---
Changes sin
Hi,
On Mon, Jun 8, 2015 at 8:47 PM, Alan Stern wrote:
> On Mon, 8 Jun 2015, Vivek Gautam wrote:
>
>> Facilitate getting required 3.3V and 1.0V VDD supply for
>> EHCI controller on Exynos.
>>
>> For example, patches for regulators' nodes:
>> c8c253f AR
Hi all,
While working on our test board with Exynos7 SoC, we see that across
suspend/resume (Suspend to RAM) the EHCI can't resume the devices connected
to HSIC phy properly.
We have been using 3.16 kernel for our development, but on the ehci-exynos
driver
side there isn't any delta that we hav
>>
>> - if (pdev->id_auto) {
>> - ida_simple_remove(&platform_devid_ida, pdev->id);
>> - pdev->id = PLATFORM_DEVID_AUTO;
>> - }
>> -
>> for (i = 0; i < pdev->num_
.
Signed-off-by: Vivek Gautam
---
drivers/usb/host/xhci-plat.c | 74 ++
1 file changed, 74 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 08d402b..c478627 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b
evels need to be
calibrated further post initialization of xHCI controller, to get
SuperSpeed operations working."
[1] https://lkml.org/lkml/2014/11/19/367
[2] https://lkml.org/lkml/2014/9/2/170; (to be specific
https://lkml.org/lkml/2014/9/10/132)
Vivek Gautam (2):
usb: host: xhci-plat: Get PHY
extra lines in the register macro definitions]
Signed-off-by: Vivek Gautam
---
drivers/phy/phy-exynos5-usbdrd.c | 219 +++---
1 file changed, 203 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
index
t; - phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
> - phy-names = "usb2-phy", "usb3-phy";
> + phys = <&usbdrd_phy1 1>;
> + phy-names = "usb3-phy&quo
On 4/3/2018 3:49 PM, Masahiro Yamada wrote:
2018-04-03 17:46 GMT+09:00 Philipp Zabel :
On Tue, 2018-04-03 at 17:30 +0900, Masahiro Yamada wrote:
2018-04-03 17:00 GMT+09:00 Philipp Zabel :
On Thu, 2018-03-29 at 15:07 +0900, Masahiro Yamada wrote:
This driver handles the reset control in a co
s since v1:
- Update unit address of DT node as per Doug's comment
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 6 --
arch/arm64/boot/dts/qcom/msm8996.dtsi| 10 ++
2 files changed, 10 insertions(+), 6 deletions(-)
Tested on DB820c. Works fine.
Tested-by: Vivek Gau
Hi,
On 6/11/2018 12:06 PM, Julien Massot wrote:
Hi,
On 5/31/2018 4:17 PM, Manu Gautam wrote:
Move from dwc3-of-simple to dwc3-qcom glue driver to
support peripheral mode which requires qscratch wrapper
programming on VBUS event.
I would like to test usb otg as peripheral role, but that's no
On 11/21/2017 02:53 PM, Manu Gautam wrote:
New version of QUSB2 PHY has some registers offset changed.
Add support to have register layout for a target and update
the same in phy_configuration.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 131 ++
Hi Manu,
On Tue, Nov 21, 2017 at 2:53 PM, Manu Gautam wrote:
> From: Vivek Gautam
>
> Move from using array of clocks to clk_bulk_* APIs that
> are available now.
>
> Signed-off-by: Vivek Gautam
> Signed-off-by: Manu Gautam
> ---
> drivers/phy/q
Hi Manu,
On Wed, Jan 3, 2018 at 4:58 PM, Manu Gautam wrote:
> New revision (v3) of QMP PHY uses different offsets
> for almost all of the registers. Hence, move these
> definitions to header file so that updated offsets
> can be added for QMP v3.
>
> Signed-off-by: Manu Gautam
> ---
> drivers/p
On Wed, Jan 3, 2018 at 4:58 PM, Manu Gautam wrote:
> PHY regulators which are enabled from power_on() must be ON
> before turning-on clocks and initializing it as part of init().
> As most of the core drivers perform power_on() after init(), move
> PHY regulators enable to com_init() and use power
on and init for QUSB2 PHY
> need to be executed together always, hence remove
> poweron callback from phy_ops and explicitly perform
> this from init, similar changes needed for poweroff.
>
> Signed-off-by: Manu Gautam
> ---
Looks good.
Reviewed-by: Vivek Gautam
Thanks
Vivek
t_list[i]);
> + goto err_rst_assert;
> + }
> }
>
> - for (i = 0; i < cfg->num_resets; i++) {
> + for (i = cfg->num_resets - 1; i >= 0; i--) {
Do we a dependency on the order in which these resets are
applied?
If
On Fri, Jan 12, 2018 at 2:16 PM, Manu Gautam wrote:
> Hi Vivek,
>
>
> On 1/12/2018 2:14 PM, Vivek Gautam wrote:
>> On Wed, Jan 3, 2018 at 4:58 PM, Manu Gautam wrote:
>>> PHY block or asynchronous reset requires signal
>>> to be asserted before de-asserting. Dr
On Wed, Jan 3, 2018 at 4:58 PM, Manu Gautam wrote:
> New version of QUSB2 PHY has some registers offset changed.
> Add support to have register layout for a target and update
> the same in phy_configuration.
>
> Signed-off-by: Manu Gautam
> ---
LGTM.
Reviewed-by: Vivek Gauta
TRL2 0x224
> +#defineQUSB2PHY_CHG_CTRL2 0x23c
nit: Replace these tabs with simple spaces.
Rest all look good.
Reviewed-by: Vivek Gautam
Thanks
Vivek
> +
> struct qusb2_phy_init_tbl {
> unsigned int offset;
> un
On 04/06/2017 03:41 PM, Kishon Vijay Abraham I wrote:
On Thursday 06 April 2017 11:21 AM, Vivek Gautam wrote:
Hi Kishon,
Here's the series with fixed checkpatch warnings/checks.
Please pick it for phy/next.
This patch series adds couple of PHY drivers for Qualcomm chipsets.
a) qcom-
The driver uses clock provider interface, and therefore
it fails to build when enabled for COMPILE_TEST, since
COMMON_CLK is not enabled at that time.
So, make PHY_QCOM_QMP depend on COMMON_CLK as well.
Cc: Fengguang Wu
Cc: Kishon Vijay Abraham I
Signed-off-by: Vivek Gautam
---
Hi Kishon
On 2017-04-10 10:52, Kishon Vijay Abraham I wrote:
On Friday 07 April 2017 01:37 AM, Vivek Gautam wrote:
The driver uses clock provider interface, and therefore
it fails to build when enabled for COMPILE_TEST, since
COMMON_CLK is not enabled at that time.
So, make PHY_QCOM_QMP depend on
for reset control array.
- Added a patch for soc/tegra/pmc driver to use the new set of
reset control array APIs.
Vivek Gautam (4):
reset: Add API to count number of reset available with device
reset: Add APIs to manage array of resets
usb: dwc3: of-simple: Add support to get resets for
Add support to get a list of resets available for the device.
These resets must be kept de-asserted until the device is
in use.
Cc: Felipe Balbi
Cc: Philipp Zabel
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/dwc3-of-simple.c | 36
1 file changed, 36
Count number of reset phandles available with the device node
to know the resets a given device has.
Cc: Philipp Zabel
Signed-off-by: Vivek Gautam
---
drivers/reset/core.c | 23 +++
include/linux/reset.h | 6 ++
2 files changed, 29 insertions(+)
diff --git a/drivers
Many devices may want to request a bunch of resets
and control them. So it's better to manage them as an
array. Add APIs to _get(), _assert(), and _deassert()
an array of reset_control.
Cc: Philipp Zabel
Signed-off-by: Vivek Gautam
---
drivers/reset/core.c
Make use of reset_control_array_*() set of APIs to manage
an array of reset controllers available with the device.
Cc: Thierry Reding
Cc: Philipp Zabel
Signed-off-by: Vivek Gautam
---
drivers/soc/tegra/pmc.c | 99 ++---
1 file changed, 36 insertions
On 04/19/2017 03:55 PM, Philipp Zabel wrote:
On Tue, 2017-04-18 at 16:51 +0530, Vivek Gautam wrote:
Count number of reset phandles available with the device node
to know the resets a given device has.
Cc: Philipp Zabel
Signed-off-by: Vivek Gautam
---
drivers/reset/core.c | 23
Hi Philipp,
On 04/19/2017 04:01 PM, Philipp Zabel wrote:
On Tue, 2017-04-18 at 16:51 +0530, Vivek Gautam wrote:
Many devices may want to request a bunch of resets
and control them. So it's better to manage them as an
array. Add APIs to _get(), _assert(), and _deassert()
an arr
On 04/19/2017 04:02 PM, Philipp Zabel wrote:
On Tue, 2017-04-18 at 16:51 +0530, Vivek Gautam wrote:
Add support to get a list of resets available for the device.
These resets must be kept de-asserted until the device is
in use.
Cc: Felipe Balbi
Cc: Philipp Zabel
Signed-off-by: Vivek Gautam
On 04/24/2017 06:15 PM, Jon Hunter wrote:
On 18/04/17 12:21, Vivek Gautam wrote:
Make use of reset_control_array_*() set of APIs to manage
an array of reset controllers available with the device.
Before we apply this patch, I need to check to see if the order of the
resets managed by the PMC
On 04/25/2017 04:24 PM, Jon Hunter wrote:
On 25/04/17 11:33, Philipp Zabel wrote:
On Tue, 2017-04-25 at 11:05 +0100, Jon Hunter wrote:
On 25/04/17 05:15, Vivek Gautam wrote:
On 04/24/2017 06:15 PM, Jon Hunter wrote:
On 18/04/17 12:21, Vivek Gautam wrote:
Make use of reset_control_array_
On Tue, Apr 25, 2017 at 4:41 PM, Jon Hunter wrote:
>
> On 25/04/17 12:06, Vivek Gautam wrote:
>> On 04/25/2017 04:24 PM, Jon Hunter wrote:
>>> On 25/04/17 11:33, Philipp Zabel wrote:
>>>> On Tue, 2017-04-25 at 11:05 +0100, Jon Hunter wrote:
>>>>>
Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.
Also updated the MAINTAINERS file to reflect the correct
directory structure for phy drivers.
Signed-off-by: Vivek Gautam
Acked-by: Heiko Stuebner
Acked-by: Viresh Kumar
Acked-by: Krzysztof
Although ULPI phy is currently being used by tusb1210,
there can be other consumers too in future. So move this
to the includes path for phy.
Signed-off-by: Vivek Gautam
Cc: Stephen Boyd
Cc: Heikki Krogerus
Cc: Kishon Vijay Abraham I
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker
Ulpi phy header is not used for anything. Remove the same
from qcom-hs and qcom-hsic phy drivers.
Signed-off-by: Vivek Gautam
Suggested-by: Stephen Boyd
Cc: Kishon Vijay Abraham I
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-arm-...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
Cc
On 05/12/2017 02:15 PM, Kishon Vijay Abraham I wrote:
Hi Vivek,
On Thursday 11 May 2017 12:17 PM, Vivek Gautam wrote:
Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.
Also updated the MAINTAINERS file to reflect the correct
directory
On 05/16/2017 03:40 PM, Kishon Vijay Abraham I wrote:
Hi Vivek,
On Thursday 11 May 2017 12:17 PM, Vivek Gautam wrote:
Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.
Also updated the MAINTAINERS file to reflect the correct
directory
Make use of reset_control_array_*() set of APIs to manage
an array of reset controllers available with the device.
Cc: Jon Hunter
Cc: Thierry Reding
Cc: Philipp Zabel
Signed-off-by: Vivek Gautam
---
drivers/soc/tegra/pmc.c | 91 +
1 file
Add support to get a list of resets available for the device.
These resets must be kept de-asserted until the device is
in use.
Cc: Felipe Balbi
Cc: Philipp Zabel
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/dwc3-of-simple.c | 27 +--
1 file changed, 25 insertions
Move clock handling after of_platform_depopulate to achieve
a sequence that is reverse of the probe sequence.
Cc: Felipe Balbi
Signed-off-by: Vivek Gautam
---
- new patch in this series.
drivers/usb/dwc3/dwc3-of-simple.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
particular order.
Cc: Felipe Balbi
Cc: Jon Hunter
Cc: Philipp Zabel
Signed-off-by: Vivek Gautam
---
drivers/reset/core.c | 204 ++
include/linux/reset.h | 93 +++
2 files changed, 297 insertions(+)
diff --git a/drivers/rese
ol array.
- Added a patch for soc/tegra/pmc driver to use the new set of
reset control array APIs.
Vivek Gautam (4):
usb: dwc3: of-simple: Re-order resource handling in remove
reset: Add APIs to manage array of resets
usb: dwc3: of-simple: Add support to get resets for the devic
Hi,
On Wed, May 31, 2017 at 7:53 PM, Jon Hunter wrote:
>
> On 22/05/17 12:23, Vivek Gautam wrote:
>> Make use of reset_control_array_*() set of APIs to manage
>> an array of reset controllers available with the device.
>>
>> Cc: Jon Hunter
>> Cc: Thierry Red
struct reset_control to
avoid having to introduce new API functions for array (de)assert/reset.
Cc: Vivek Gautam
Cc: Jon Hunter
Signed-off-by: Philipp Zabel
---
drivers/reset/core.c | 225 ++
include/linux/reset.h | 44 +++---
2 files changed
of APIs
for reset control array.
- Added a patch for soc/tegra/pmc driver to use the new set of
reset control array APIs.
Philipp Zabel (2):
reset: use kref for reference counting
reset: hide reset control arrays behind struct reset_control
Vivek Gautam (4):
reset: Add APIs to m
Hi Philipp,
On 06/19/2017 05:48 PM, Philipp Zabel wrote:
Hi Vivek,
On Tue, 2017-06-13 at 12:16 +0530, Vivek Gautam wrote:
[...]
@@ -102,18 +94,6 @@ static inline struct reset_control
*__devm_reset_control_get(
return optional ? NULL : ERR_PTR(-ENOTSUPP);
}
-static inline
Fixing the clk enable failure path in qcom_qmp_phy_init()
and cleanup the reset control deassertion failure path in
qcom_qmp_phy_com_init().
Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Cc: Kishon Vijay Abraham I
Signed-off-by: Vivek Gautam
---
d
Hi Kishon,
On Tue, Jun 20, 2017 at 11:27 AM, Vivek Gautam
wrote:
> Fixing the clk enable failure path in qcom_qmp_phy_init()
> and cleanup the reset control deassertion failure path in
> qcom_qmp_phy_com_init().
>
> Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driv
On Wed, Aug 2, 2017 at 10:39 AM, Kishon Vijay Abraham I wrote:
> Vivek,
>
> On Monday 31 July 2017 10:58 AM, Vivek Gautam wrote:
>> Hi Kishon,
>>
>>
>> On Tue, Jun 20, 2017 at 11:27 AM, Vivek Gautam
>> wrote:
>>> Fixing the clk enable failure path
Hi Adam,
On Mon, Aug 28, 2017 at 10:05 PM, Adam Wallis wrote:
> The dma ops from the parent DWC device are not getting passed to the
> child xhci-hcd device. This patch makes use of
> platform_device_register_full to set the DMA ops. For the DT/OF case,
> dma_ops were still null after the the de
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