Adding base address information and required platform data
support for enabling USB DRD phy on exynos5250 SOC.
Signed-off-by: Vivek Gautam
---
arch/arm/boot/dts/exynos5250.dtsi|3 ++-
arch/arm/mach-exynos/include/mach/regs-pmu.h |4
arch/arm/mach-exynos/setup-usb-phy.c
> Signed-off-by: Praveen Paneri
> Acked-by: Heiko Stuebner
> Acked-by: Kyungmin Park
I have tested this patch-series for S3C6410 and S5PV310 for gadget functioning.
Looks good to me.
Tested-by: Vivek Gautam
> ---
> .../devicetree/bindings/usb/samsung-usbphy.txt | 1
Hi,
On Tue, Nov 6, 2012 at 10:13 PM, Felipe Balbi wrote:
> On Tue, Nov 06, 2012 at 08:58:49PM +0530, Vivek Gautam wrote:
>> Adding DWC3 device tree node for Exynos5250 along with the
>> device address and clock support needed for the controller.
>>
>>
Hi,
On Wed, Nov 7, 2012 at 5:10 AM, Sylwester Nawrocki
wrote:
>
> Hi,
>
> I have a few comments. Please see below...
>
>
> On 11/06/2012 04:36 PM, Vivek Gautam wrote:
>>
>> Adding support for USB3.0 phy for dwc3 controller on
>> exynso5250 SOC.
>
>
Hi,
On Wed, Nov 7, 2012 at 10:48 PM, Tomasz Figa wrote:
> Hi Vivek, Felipe,
>
> On Wednesday 07 of November 2012 18:43:22 Felipe Balbi wrote:
>> Hi,
>>
>> On Wed, Nov 07, 2012 at 06:55:03PM +0530, Vivek Gautam wrote:
>> > Hi,
>> >
>> >
Changes from v1:
- Changed the device node names from 'ehci' and 'ohci' to
'usb@1211' and 'usb@1212' as per discussion for the
change 'http://www.spinics.net/lists/linux-usb/msg73993.html'
- Rebased on for-next branch of linux-samsu
Adding EHCI device tree node for Exynos5250 along with
the device base adress and gpio line for vbus.
Signed-off-by: Vivek Gautam
Acked-by: Jingoo Han
---
.../devicetree/bindings/usb/exynos-usb.txt | 25
arch/arm/boot/dts/exynos5250-smdk5250.dts |4
Adding OHCI device tree node for Exynos5250 along with
the device base address.
Signed-off-by: Vivek Gautam
Acked-by: Jingoo Han
---
.../devicetree/bindings/usb/exynos-usb.txt | 15 +++
arch/arm/boot/dts/exynos5250.dtsi |6 ++
arch/arm/mach-exynos
Hi all,
On Thu, Nov 8, 2012 at 12:24 PM, Vivek Gautam wrote:
> Adding EHCI device tree node for Exynos5250 along with
> the device base adress and gpio line for vbus.
>
> Signed-off-by: Vivek Gautam
> Acked-by: Jingoo Han
> ---
> .../devicetree/bindings/usb/exynos-u
Hi all,
On Thu, Nov 8, 2012 at 12:24 PM, Vivek Gautam wrote:
> Adding OHCI device tree node for Exynos5250 along with
> the device base address.
>
> Signed-off-by: Vivek Gautam
> Acked-by: Jingoo Han
> ---
> .../devicetree/bindings/usb/exynos-usb.txt | 15 ++
Adding EHCI device tree node for Exynos5250 along with
the device base adress and gpio line for vbus.
Signed-off-by: Vivek Gautam
Acked-by: Jingoo Han
---
.../devicetree/bindings/usb/exynos-usb.txt | 25
arch/arm/boot/dts/exynos5250-smdk5250.dts |4
Adding OHCI device tree node for Exynos5250 along with
the device base address.
Signed-off-by: Vivek Gautam
Acked-by: Jingoo Han
---
.../devicetree/bindings/usb/exynos-usb.txt | 15 +++
arch/arm/boot/dts/exynos5250.dtsi |6 ++
arch/arm/mach-exynos
Tested with required driver DT patches for dwc3-exynos:
http://www.spinics.net/lists/linux-usb/msg73857.html
and USB 3.0 phy support patches:
https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-November/021926.html
Vivek Gautam (1):
ARM: Exynos5250: Enabling dwc3-exynos driver
.../
Adding DWC3 device tree node for Exynos5250 along with the
device address and clock support needed for the controller.
Signed-off-by: Vivek Gautam
---
.../devicetree/bindings/usb/exynos-usb.txt | 14 +++
arch/arm/boot/dts/exynos5250.dtsi |6 +
arch/arm
d of in any glue layer.
- Splitting the patch:
[PATCH 4/4] usb: phy: samsung: Enable runtime power management on samsung-usb
into required number to bifurcate functionality.
Vivek Gautam (11):
usb: phy: Add APIs for runtime power management
USB: dwc3: Adjust runtime pm to allow autosuspend
By enabling runtime pm in this driver allows users of
xhci-plat to enter into runtime pm. This is not full
runtime pm support (AKA xhci-plat doesn't actually power
anything off when in runtime suspend mode) but,
just basic enablement.
Signed-off-by: Vivek Gautam
CC: Doug Anderson
---
dr
Enable autosuspending of Samsung usb2.0 PHY
Signed-off-by: Vivek Gautam
---
drivers/usb/phy/phy-samsung-usb2.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/phy/phy-samsung-usb2.c
b/drivers/usb/phy/phy-samsung-usb2.c
index 45ffe03..d378fe9 100644
The PHY controller can choose between ref_pad_clk (XusbXTI-external PLL),
or EXTREFCLK (XXTI-internal clock crystal) to generate the required clock.
Adding the provision for ref_pad_clk here.
Signed-off-by: Vivek Gautam
---
drivers/usb/phy/phy-samsung-usb3.c | 46
Enable autosuspending of Samsung usb3.0 PHY
Signed-off-by: Vivek Gautam
---
drivers/usb/phy/phy-samsung-usb3.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/phy/phy-samsung-usb3.c
b/drivers/usb/phy/phy-samsung-usb3.c
index 54f6418..a713585 100644
Enabling runtime power management on dwc3-exynos
letting dwc3 controller to be autosuspended on exynos
platform when not in use.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/dwc3-exynos.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc3
Right now it doesn't handle full runtime suspend/resume
functionality. However it allows to handle PHYs' sleep
and wakeup across runtime suspend/resume.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/core.c | 43 +++
1 files changed, 43
Adding APIs to handle runtime power management on PHY
devices. PHY consumers may need to wake-up/suspend PHYs
when they work across autosuspend.
Signed-off-by: Vivek Gautam
---
include/linux/usb/phy.h | 141 +++
1 files changed, 141 insertions(+), 0
Allow dwc3 to enable auto power management only after its PHYs
are initialized so that any further PHY handling by dwc3's
runtime power management callbacks is fine.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/core.c | 18 +-
1 files changed, 9 insertions(+), 9 dele
The current code in the dwc3 probe effectively disables runtime pm
from ever working because it calls a get() that was never put() until
device removal. Change the runtime pm code to match the standard
formula and allow runtime pm to function.
Signed-off-by: Vivek Gautam
CC: Doug Anderson
Hi,
On Tue, Apr 2, 2013 at 1:53 PM, Felipe Balbi wrote:
> On Mon, Apr 01, 2013 at 07:24:00PM +0530, Vivek Gautam wrote:
>> Adding APIs to handle runtime power management on PHY
>> devices. PHY consumers may need to wake-up/suspend PHYs
>> when they work across autosuspend
Hi,
On Tue, Apr 2, 2013 at 5:40 PM, Felipe Balbi wrote:
> Hi,
>
> On Tue, Apr 02, 2013 at 04:04:01PM +0530, Vivek Gautam wrote:
>> > On Mon, Apr 01, 2013 at 07:24:00PM +0530, Vivek Gautam wrote:
>> >> Adding APIs to handle runtime power management on PHY
>>
Hi Balbi,
On Tue, Apr 2, 2013 at 2:02 PM, Felipe Balbi wrote:
> Hi,
>
> On Mon, Apr 01, 2013 at 07:24:03PM +0530, Vivek Gautam wrote:
>> +#else
>> +#define dwc3_runtime_suspend NULL
>> +#define dwc3_runtime_resume NULL
>
> this #else b
Hi Felipe,
On Tue, Apr 2, 2013 at 1:59 PM, Felipe Balbi wrote:
> On Mon, Apr 01, 2013 at 07:24:01PM +0530, Vivek Gautam wrote:
>> The current code in the dwc3 probe effectively disables runtime pm
>> from ever working because it calls a get() that was never put() until
&g
Hi Kishon,
On Wed, Apr 3, 2013 at 10:38 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
>
> On Monday 01 April 2013 07:24 PM, Vivek Gautam wrote:
>>
>> Adding APIs to handle runtime power management on PHY
>> devices. PHY consumers may need to wake-up/suspend
Hi Felipe,
On Wed, Apr 3, 2013 at 1:45 PM, Felipe Balbi wrote:
> Hi,
>
> On Wed, Apr 03, 2013 at 11:48:39AM +0530, Vivek Gautam wrote:
>> >> Adding APIs to handle runtime power management on PHY
>> >> devices. PHY consumers may need to wake-up/suspend
Hi,
On Wed, Apr 3, 2013 at 7:26 PM, Felipe Balbi wrote:
> Hi,
>
> On Wed, Apr 03, 2013 at 04:54:14PM +0300, Felipe Balbi wrote:
>> > >> >> +static inline void usb_phy_autopm_enable(struct usb_phy *x)
>> > >> >> +{
>> > >> >> + if (!x || !x->dev) {
>> > >> >> + dev_err(x->dev,
On Wed, Apr 3, 2013 at 7:48 PM, Felipe Balbi wrote:
> Hi,
>
> On Wed, Apr 03, 2013 at 07:40:44PM +0530, Vivek Gautam wrote:
>> >> > >> >> +static inline void usb_phy_autopm_enable(struct usb_phy *x)
>> >> > >> >> +{
>> >>
es for 3.10, sorry.
>
> Sarah Sharp
>
> On Mon, Apr 01, 2013 at 07:23:59PM +0530, Vivek Gautam wrote:
>> This patch-series enables runtime power management on xhci-plat,
>> dwc3-core, dwc3-exynos as well as on Samsung's USB 2.0 type and
>> USB 3.0 type PHYs.
&g
Hi Kukjin,
On Fri, Mar 15, 2013 at 1:26 PM, Vivek Gautam wrote:
> Based on 'for-next' of linux-samsung tree with following patches
> from Doug on top:
> usb: Document clocks in samsung, exynos4210-ehci/ohci bindings
> ARM: dts: add usb 2.0 clock references to exynos525
Hi Kukjin,
On Fri, Mar 15, 2013 at 1:32 PM, Vivek Gautam wrote:
> This patch-set is in continuation with patch-series:
> [PATCH v4 0/4] Enable ehci, ohci and dwc3 devices on exynos5250
> out of which follwowing patches have been picked up:
> ARM: Exynos5250: Enabling ehci-s5p
On Thu, Apr 4, 2013 at 12:40 PM, Felipe Balbi wrote:
> On Thu, Apr 04, 2013 at 10:34:57AM +0530, Vivek Gautam wrote:
>> Hi Sarah,
>>
>>
>> On Wed, Apr 3, 2013 at 10:57 PM, Sarah Sharp
>> wrote:
>> > Question: Do you still need this patch for 3.10?
&g
Hi,
On Thu, Apr 4, 2013 at 12:48 PM, Felipe Balbi wrote:
> Hi,
>
> On Wed, Apr 03, 2013 at 02:14:02PM -0400, Alan Stern wrote:
>> > > Lets suppose DWC3 enables runtime_pm on USB 2 type phy,
>> > > it will try to go into suspend state and thereby call runtime_suspend(),
>> > > if any.
>> > > And
xes issues with null pointer dereferencing in
s5p_ehci_shutdown(), s5p_ehci_suspend(), s5p_ehci_resume().
Signed-off-by: Vivek Gautam
CC: Manjunath Goudar
CC: Arnd Bergmann
CC: Jingoo Han
---
drivers/usb/host/ehci-s5p.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/d
Hi,
On Tue, Apr 9, 2013 at 6:01 PM, Sergei Shtylyov
wrote:
> Hello.
>
>
> On 09-04-2013 13:21, Vivek Gautam wrote:
>
>> 7edb3da makes ehci-s5p as a separate driver. But,
>
>
>Please also provide the summary line of that commit in parens.
Sure, will add
is fixes issues with null pointer dereferencing in
s5p_ehci_shutdown(), s5p_ehci_suspend(), s5p_ehci_resume().
Signed-off-by: Vivek Gautam
CC: Manjunath Goudar
CC: Arnd Bergmann
CC: Jingoo Han
---
Based on 'usb-next'
drivers/usb/host/ehci-s5p.c |2 +-
1 files changed, 1
Hi,
On Thu, Apr 4, 2013 at 8:16 PM, Alan Stern wrote:
Apologies for delay in replying.
> On Thu, 4 Apr 2013, Felipe Balbi wrote:
>
>> > >> Some subsystems handle this issue by calling pm_runtime_get_sync()
>> > >> before probing a driver and pm_runtime_put_sync() after unbinding the
>> > >> dr
Hi,
On Tue, Apr 23, 2013 at 10:23 PM, Alan Stern wrote:
> On Tue, 23 Apr 2013, Vivek Gautam wrote:
>
>> >> Alright, so here's my understanding:
>> >>
>> >> I suggested letting e.g. DWC3 enable the PHY's runtime_pm; Alan said
>> >>
On Tue, Apr 23, 2013 at 11:42 PM, Alan Stern wrote:
> On Tue, 23 Apr 2013, Vivek Gautam wrote:
>
>> Hi,
>>
>>
>> On Tue, Apr 23, 2013 at 10:23 PM, Alan Stern
>> wrote:
>> > On Tue, 23 Apr 2013, Vivek Gautam wrote:
>> >
>> >> >
Hi Felipe,
Commit 388e5c51135f817f01177c42261f1116a6d7f2ad usb: dwc3: remove dwc3
dependency on host AND gadget
by me breaks compilation when USB_DWC3=y, USB=y but USB_GADGET=m,
additionally when either of USB_DWC3_GADGET=y or USB_DWC3_DUAL_ROLE=y :-(
I had some confusion with this actually
in certain direction.
>
> On Thu, May 9, 2013 at 12:34 AM, Vivek Gautam
> wrote:
>> Hi Felipe,
>>
>> Commit 388e5c51135f817f01177c42261f1116a6d7f2ad usb: dwc3: remove dwc3
>> dependency on host AND gadget
>> by me breaks compilation when USB_DWC
Hi Felipe,
On Thu, May 9, 2013 at 8:18 PM, Felipe Balbi wrote:
> Hi,
>
> On Wed, May 08, 2013 at 10:04:56PM +0530, Vivek Gautam wrote:
>> Commit 388e5c51135f817f01177c42261f1116a6d7f2ad usb: dwc3: remove
>> dwc3 dependency on host AND gadget
>> by me breaks compila
Hi Dongjin,
On Mon, May 13, 2013 at 11:55 PM, Dongjin Kim wrote:
> This patch adds usb host phy (USB 2.0 PHY) support for Samsung Exynos4X12 SoC.
> New functions, samsung_exynos4x12_usb2phy_enable/_disable and selecting
> reference clock, for Exynos4X12 are added. Since it has different register
Hi,
On Fri, May 10, 2013 at 8:35 PM, Vivek Gautam wrote:
> Hi Felipe,
>
>
> On Thu, May 9, 2013 at 8:18 PM, Felipe Balbi wrote:
>> Hi,
>>
>> On Wed, May 08, 2013 at 10:04:56PM +0530, Vivek Gautam wrote:
>>> Commit 388e5c51135f817f01177c42261f1116a6d7f2a
71a5e61 usb: chipidea: fix and improve dependencies if usb host or gadget
support is built as module
Let us limit the DWC3 mode to depend on corresponding usb-subsystem
and USB_DWC3.
Signed-off-by: Vivek Gautam
Cc: Felipe Balbi
Cc: Fengguang Wu
---
drivers/usb/dwc3/Kconfig |6 +++---
1 fi
Add device tree nodes for USB 3.0 PHY present alongwith
USB 3.0 controller Exynos 5420 SoC. This phy driver is
based on generic phy framework.
Signed-off-by: Vivek Gautam
---
arch/arm/boot/dts/exynos5420.dtsi | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff
Update device tree bindings for DWC3 controller and
USB 3.0 phy present on Exynos 5250 SoC, to start using
the phy driver based on generic phy framework.
Signed-off-by: Vivek Gautam
---
arch/arm/boot/dts/exynos5250.dtsi | 16 ++--
1 files changed, 6 insertions(+), 10 deletions
nd using them for one time
PHY-initialization and deinitialization.
- Filtering out the PHY 'power-on' and 'power-off' sequence to '.power_on"
and ".power_off" callbacks.
- Removed drivers/usb/phy/phy-samsung-usb3.c driver and related code.
3) fixes
Add device tree nodes for DWC3 controller present on
Exynos 5420 SoC, to enable support for USB 3.0.
Signed-off-by: Vivek Gautam
---
arch/arm/boot/dts/exynos5420.dtsi | 38 +++-
1 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts
framework.
Signed-off-by: Vivek Gautam
---
.../devicetree/bindings/phy/samsung-phy.txt| 43 ++
drivers/phy/Kconfig|8 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos5-usb3.c | 545
Hi Kishon,
On Wed, Dec 4, 2013 at 7:58 PM, Kishon Vijay Abraham I wrote:
> Hi Vivek,
>
> On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote:
>>> On Wed, Nov 20, 201
l on Exynos5250 currently.
Ok, will merge it with patch #1
[PATCH v2 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Thanks for pointing out.
>
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
>
> On Wednesday, Decem
unsigned int delay, bool
> warm);
> -
> /* Is a USB 3.0 port in the Inactive or Complinance Mode state?
> * Port worm reset is required to recover
> */
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc&qu
generic PHY framework
http://lwn.net/Articles/575586/
Vivek Gautam (4):
phy: Add provision for tuning phy.
xhci: Add quirk for DWC3-Exynos controller
xhci: Tune PHY for the DWC3-Exynos host controller
phy-exynos-usb3: Fine tune LOS levels for exynos5420
drivers/phy/phy-core.c
Some PHY controllers may need to tune PHY post-initialization,
so that the PHY consumers can call phy-tuning at appropriate
point of time.
Signed-off-by: vivek Gautam
---
drivers/phy/phy-core.c | 20
include/linux/phy/phy.h |7 +++
2 files changed, 27 insertions
ndary HCD of XHCI.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/host.c |7 ++
drivers/usb/host/xhci-plat.c | 43 -
include/linux/usb/hcd.h |1 +
3 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/hos
-off-by: Vivek Gautam
---
drivers/phy/phy-exynos5-usb3.c | 107
1 files changed, 107 insertions(+), 0 deletions(-)
diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c
index 2bafc9d..669f998 100644
--- a/drivers/phy/phy-exynos5-usb3
controller has been reset.
Adding a xHCI quirk for this purpose.
Signed-off-by: Vivek Gautam
---
drivers/usb/host/xhci-plat.c | 19 +++
drivers/usb/host/xhci.h |1 +
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb
Hi,
On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
wrote:
> Hi,
Thanks for reviewing this.
>
> On Tue, Dec 10, 2013 at 04:25:23PM +0530, Vivek Gautam wrote:
>> Some PHY controllers may need to tune PHY post-initialization,
>> so that the PHY consumers can call phy-
Hi,
On Wed, Dec 11, 2013 at 1:39 PM, Heikki Krogerus
wrote:
> Hi,
>
> On Wed, Dec 11, 2013 at 12:08:04PM +0530, Vivek Gautam wrote:
>> On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
>> > I think "setup" instead of "tune" is much more clear and re
Hi Kishon,
On Wed, Dec 11, 2013 at 1:47 PM, Kishon Vijay Abraham I wrote:
> On Wednesday 11 December 2013 12:08 PM, Vivek Gautam wrote:
>> Hi,
>>
>>
>> On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
>> wrote:
>>> Hi,
>>
>> Thanks for re
Hi All,
On Wed, Dec 4, 2013 at 3:39 PM, Vivek Gautam wrote:
> Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
> The new driver uses the generic PHY framework and will interact
> with DWC3 controller present on Exynos5 series of SoCs.
> Thereby, removing old phy-
Hi Felipe,
On Mon, Dec 23, 2013 at 10:18 PM, Felipe Balbi wrote:
> Hi,
>
> On Mon, Dec 23, 2013 at 02:41:15PM +0530, Vivek Gautam wrote:
>> On Wed, Dec 4, 2013 at 3:39 PM, Vivek Gautam
>> wrote:
>> > Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs
>otg)
> - exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
> -
> - if (exynos_ehci->phy)
> - usb_phy_shutdown(exynos_ehci->phy);
> + exynos_phys_off(exynos_ehci->phy);
>
> clk_disable_unpre
+ EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL);
> + writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
> + break;
> + case EXYNOS5250_HSIC0:
> + case EXYNOS5250_HSIC1:
> + hsic = (EXYNOS_52
Hi Kishon,
On Tue, Dec 24, 2013 at 11:15 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
>
> On Thursday 05 December 2013 01:44 PM, Vivek Gautam wrote:
>>
>> Hi Kishon,
>>
>>
>> On Wed, Dec 4, 2013 at 7:58 PM, Kishon Vijay Abraham I
>> wrote:
>>
HI Kishon
On Tue, Jan 7, 2014 at 3:19 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 30 December 2013 03:13 PM, Vivek Gautam wrote:
>> Hi Kishon,
>>
>>
>> On Tue, Dec 24, 2013 at 11:15 PM, Kishon Vijay Abraham I
>> wrote:
>>> Hi,
>>
framework.
Signed-off-by: Vivek Gautam
---
Changes from v2:
1) Added support for multiple PHYs (UTMI+ and PIPE3) and
related changes in the driver structuring.
2) Added a xlate function to get the required phy out of
number of PHYs in mutiple PHY scenerio.
3) Changed the names of few structures and
ons of the IP we'll have separate bits to control usb3 and usb2.
>
> Ok, i will prepare the next patchset for separating out the possible
> code based on
> the UTMI+ or PIPE3 phys. Though when experimenting with the PHY
> settings i can see
> there's little of such code :-)
&
On Mon, Jan 20, 2014 at 7:12 PM, Vivek Gautam wrote:
> Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
> The new driver uses the generic PHY framework and will interact
> with DWC3 controller present on Exynos5 series of SoCs.
> Thereby, removing old phy-samsung-usb
usb_phy_set_suspend(dwc->usb2_phy, 0);
>> usb_phy_set_suspend(dwc->usb3_phy, 0);
>>
>> + if (dwc->usb2_generic_phy)
>> + phy_power_on(dwc->usb2_generic_phy);
>> + if (dwc->usb3_generic_phy)
>> + phy_power_on(dwc->us
Hi Kishon,
On Mon, Jan 27, 2014 at 2:27 PM, Kishon Vijay Abraham I wrote:
> Hi,
Thanks for review. Please find my answers inline below.
>
> On Monday 20 January 2014 07:12 PM, Vivek Gautam wrote:
>> Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
>> Th
Hi,
On Thu, Jan 30, 2014 at 11:48 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 30 January 2014 09:49 AM, Vivek Gautam wrote:
>> Hi Kishon,
>>
>>
>> On Mon, Jan 27, 2014 at 2:27 PM, Kishon Vijay Abraham I
>> wrote:
>>> Hi,
>>
>
Hi Heikki,
On Fri, Oct 17, 2014 at 8:09 PM, Heikki Krogerus
wrote:
> Removes the need for the phys to be aware of their users
> even when not using DT. The method is copied from clkdev.c.
>
> Signed-off-by: Heikki Krogerus
> Tested-by: Vivek Gautam
> ---
> Document
extra lines in the register macro definitions]
Signed-off-by: Vivek Gautam
---
drivers/phy/phy-exynos5-usbdrd.c | 219 +++---
1 file changed, 203 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
index
.
Signed-off-by: Vivek Gautam
---
drivers/usb/host/xhci-plat.c | 74 ++
1 file changed, 74 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 3d78b0c..5207d5b 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b
ng this controller operates at High-Speed
by default, so it detects even Super-speed devices as high-speed ones.
Certain PHY parameters like Tx LOS levels and Boost levels need to be
calibrated further post initialization of xHCI controller, to get
SuperSpeed operations working."
[1] http
On Tue, Nov 11, 2014 at 12:12 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Friday 31 October 2014 06:03 PM, Vivek Gautam wrote:
>> Hi Heikki,
>>
>>
>> On Fri, Oct 17, 2014 at 8:09 PM, Heikki Krogerus
>> wrote:
>>> Removes the need for the phys to
Hi Kishon,
On Tue, Nov 11, 2014 at 2:20 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 11 November 2014 02:07 PM, Vivek Gautam wrote:
>> On Tue, Nov 11, 2014 at 12:12 PM, Kishon Vijay Abraham I
>> wrote:
>>> Hi,
>>>
>>> On Friday 31 Oc
Using the same driver name for platform driver and a globally defined,
structure used throughout the file, looks a bit unpleasing.
So changing the driver name from "samsung_usb2_phy_driver" to
"samsung_usb2_phy"
Signed-off-by: Vivek Gautam
Cc: Kamil Debski
Cc: Ki
Hi Heikki, Kishon,
On Tue, Nov 11, 2014 at 2:23 PM, Vivek Gautam wrote:
> Hi Kishon,
>
>
> On Tue, Nov 11, 2014 at 2:20 PM, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Tuesday 11 November 2014 02:07 PM, Vivek Gautam wrote:
>>> On Tue, Nov 11, 2
Hi,
On Fri, Oct 31, 2014 at 7:21 PM, Sergei Shtylyov
wrote:
> Hello.
>
> On 10/31/2014 4:26 PM, Vivek Gautam wrote:
>
>> The host controller by itself may sometimes need to handle PHY
>> and re-initialize it to re-configure some of the PHY parameters
>> to g
Hi Felipe,
On Fri, Oct 31, 2014 at 6:56 PM, Vivek Gautam wrote:
> The host controller by itself may sometimes need to handle PHY
> and re-initialize it to re-configure some of the PHY parameters
> to get full support out of the PHY controller.
> Therefore, facilitate getting the
On Fri, Nov 14, 2014 at 7:45 PM, Heikki Krogerus
wrote:
> Hi Vivek,
>
> On Thu, Nov 13, 2014 at 07:03:01PM +0530, Vivek Gautam wrote:
>> Hi Heikki, Kishon,
>>
>> How about adding the change in attached patch [1] on top of this patch.
>> Just introduced the phy
On Mon, Nov 17, 2014 at 9:46 PM, Sergei Shtylyov
wrote:
> Hello.
>
> On 11/17/2014 9:36 AM, Vivek Gautam wrote:
>
>>>> The host controller by itself may sometimes need to handle PHY
>>>> and re-initialize it to re-configure some of the PHY parameters
>
/10/31/266
If you want here's my tested-by, again for entire series.
Tested-by: Vivek Gautam
>
> Changes since v4:
> - Support for static lookups is dropped. The lookups can be now only
> be created with phy_create_lookup()
>
> Changes since v3:
> - We can't
is series only so as to avoid having 'n' number of dependencies.
The USB driver patches in this series were part of [1] sent earlier.
[1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
https://lkml.org/lkml/2014/10/7/191
Vivek Gautam (11):
pinctrl: exynos: Add
USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Vivek Gautam
Cc: Linus Walleij
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 12
1 file changed, 12
There's no need to keep one local variable for clock, and
then assign the same to 'clk' member of dwc3_exynos.
Just cleaning it up.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/dwc3-exynos.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/d
DWC3 controller on Exynos SoC series have separate control for
suspend clock which replaces pipe3_rx_pclk as clock source to
a small part of DWC3 core that operates when SS PHY is in its
lowest power state (P3) in states SS.disabled and U3.
Suggested-by: Anton Tikhomirov
Signed-off-by: Vivek
DWC3 controller on Exynos7 SoC has separate control for
AXI UpScaler which connects DWC3 DRD controller to AXI bus.
Get the gate clock for the same to control it across power
cycles.
Suggested-by: Anton Tikhomirov
Signed-off-by: Vivek Gautam
---
Documentation/devicetree/bindings/usb/exynos
: Anton Tikhomirov
Signed-off-by: Vivek Gautam
---
.../devicetree/bindings/phy/samsung-phy.txt|6 ++
drivers/phy/phy-exynos5-usbdrd.c | 104
2 files changed, 92 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy
Some Exynos boards have a separate regulator controlling a
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
vbus supply on the port.
Signed-off-by: Vivek Gautam
---
drivers/phy/phy-exynos5-usbdrd.c | 32
This PHY controller is also present on Exynos7 platform
in arch-exynos family.
So PHY_EXYNOS5_USBDRD should now depend on ARCH_EXYNOS.
Signed-off-by: Vivek Gautam
---
drivers/phy/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/Kconfig b/drivers/phy
Adding required gate clocks for USB3.0 DRD controller
present on Exynos7.
Signed-off-by: Vivek Gautam
---
drivers/clk/samsung/clk-exynos7.c | 64 +++
include/dt-bindings/clock/exynos7-clk.h |9 -
2 files changed, 72 insertions(+), 1 deletion(-)
diff
BUS1 pinctrl provides gpios for usb and power regulator
available on exynos7-espresso board. So add relevant device
node for pinctrl-bus1.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 26 +++
arch/arm64
401 - 500 of 868 matches
Mail list logo
